View MCIMX253CJM4A_6340368.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor data sheet: technical data document number: imx25cec rev. 9, 06/2012 mcimx25 package information plastic package case 5284 17 x 17 mm, 0.8 mm pitch case 2107 12 x 12 mm, 0.5 mm pitch ordering information see table 1 on page 3 for ordering information. ? 2012 freescale semiconductor, inc. all rights reserved. 1 introduction the i.mx25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets. at the core of the i.mx25 is freescale's fast, proven, power-efficient implementation of the arm926ej-s core, with speeds of up to 400 mhz. the i.mx25 includes support for up to 133 mhz ddr2 memory, integrated 10/100 ethernet mac, and two on-chip usb phys. the device is suitable for a wide range of applications, including the following: ? graphical remote controls ? human machine interface (hmi) ? residential and commercial control panels ? residential gateway (smart metering) ? handheld scanners and printers ? electronic point-of-sale terminals ? patient-monitoring devices i.mx25 applications processor for consumer and industrial products silicon version 1.2 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1. special signal considerations . . . . . . . . . . . . . . . . 9 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. i.mx25 chip-level conditions . . . . . . . . . . . . . . . . 11 3.2. supply power-up/power-down requirements and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3. power characteristics . . . . . . . . . . . . . . . . . . . . . . 18 3.4. thermal characteristics . . . . . . . . . . . . . . . . . . . . 19 3.5. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6. ac electrical characteristics . . . . . . . . . . . . . . . . 24 3.7. module timing and electrical parameters . . . . . . 41 4. package information and contact assignment . . . . . . 124 4.1. 400 mapbga?case 17x17 mm, 0.8 mm pitch . 124 4.2. ground, power, sense, and reference contact assignments case 17x17 mm, 0.8 mm pitch . . . 125 4.3. signal contact assignments?17 x 17 mm, 0.8 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.4. i.mx25 17x17 package ball map . . . . . . . . . . . . 135 4.5. 347 mapbga?case 12 x 12 mm, 0.5 mm pitch 138 4.6. ground, power, sense, and reference contact assignments case 12x12 mm, 0.5 mm pitch . . . 139 4.7. signal contact assignments?12 x 12 mm, 0.5 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.8. i.mx25 12x12 package ball map . . . . . . . . . . . . 148 5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
i.mx25 applications processor for consumer and industrial products, rev. 9 2 freescale semiconductor features of the i.mx25 processor include the following: ? advanced power management?the heart of th e device is a level of power management throughout the ic that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-po wer modes. power manage ment techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations. ? multimedia powerhouse?the multimedia performance of the i.mx25 processor is boosted by a 16 kb l1 instruction and data cache system and further enhanced by an lcd controller (with alpha blending), a cmos image sensor interface, an a/d controller (integrated touchscreen controller), and a programmable smart dma (sdma) controller. ? 128 kbytes on-chip sram?the additional 128 kbyte on-chip sram makes the device ideal for eliminating external ram in applications with small footprint rtos. the on-chip sram allows the designer to enable an ultra low power lcd refresh. ? interface flexibility?the device interface supports connection to all common types of external memories: mobileddr, ddr, ddr2, nor flash, psram, sdram and sram, nand flash, and managed nand. ? increased security?because the need for advanced security for tethered and untethered devices continues to increase, the i.mx25 processor delivers hardware-enabled security features that enable secure e-commerce, digital rights manage ment (drm), information encryption, robust tamper detection, secure boot, and secure software downloads. ? on-chip phy?the device includes an hs usb otg phy and fs usb host phy. ? fast ethernet?for rapid external communication, a fast ethernet controller (fec) is included. ? i.mx25 only supports little endian mode.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 3 1.1 ordering information table 1 provides ordering information for the i.mx25. table 1. ordering information description part number silicon version projected temperature range ( c) package ballmap i.mx253 mcimx253dvm4 1.1 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257dvm4 1.1 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx253 mcimx253cvm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257cvm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx258 mcimx258cvm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx253 mcimx253djm4 1.1 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257djm4 1.1 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx253 mcimx253cjm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257cjm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx258 mcimx258cjm4 1.1 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx253 mcimx253djm4a 1.2 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257djm4a 1.2 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257djm4ar2 1.2 ?20 to +70 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx253 MCIMX253CJM4A 1.2 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257cjm4a 1.2 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx258 mcimx258cjm4a 1.2 ?40 to +85 17 x 17 mm, 0.8 mm pitch, mapbga-400 table 103 i.mx257 mcimx257cjn4a 1.2 ?40 to +85 12 x 12mm, 0.5mm pitch, mapbga-347 table 107
i.mx25 applications processor for consumer and industrial products, rev. 9 4 freescale semiconductor table 2 shows the functional differences between the different parts in the i.mx25 family. table 2. i.mx25 parts functional differences features mcimx253 mcimx257 mcimx258 core arm926ej-s? arm926ej-s? arm926ej-s? cpu speed 400 mhz 400 mhz 400 mhz l1 i/d cache 16k i/d 16k i/d 16k i/d on-chip sram 128 kb 128 kb 128 kb pata /c e -ata yes yes yes lcd controller yes yes yes touchscreen ? yes yes csi ? yes yes flexcan (2) ? yes yes esai ? yes yes sim (2) ? yes yes security ? ? yes 10/100 ethernet yes yes yes hs usb 2.0 otg + phy yes yes yes hs usb 2.0 host + phy yes yes yes 12-bit adc yes yes yes sd/sdio/mmc (2) yes yes yes external memory controller yes yes yes i 2 c (3) yes yes yes ssi/i2s (2) yes yes yes cspi (2) yes yes yes uart (5) yes yes yes
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 5 1.2 block diagram figure 1 shows the simplified interface block diagram. figure 1. i.mx25 simplified interface block diagram arm ? processor domain (ap) external memory interface (emi) smart dma sdma peripherals arm peripherals arm9 internal memory ddr2 / mddr nor flash/ nand flash audio/power management arm926ej-s spba cspi(2) uart(3) platform bluetooth mmc/sdio keypad max aips(2) jtag access. conn. lcd display 1 ext. graphics accelerator timers gpt(4) rtc wdog 1-wire i 2 c(3) pwm(4) kpp uart(2) fusebox shared domain psram or wlan scc flexcan(2) hs usb otg ata iim cspi rticv3 esdhc(2) audmux l1 i/d cache etm av i c rngb epit(2) ect iomux fec hs usb otg phy hs usb host ssi(1) ssi gpio(3) ect lcdc / csi csi slcdc camera sensor adc/tsc dryice esai sim(2) fs usb host phy
i.mx25 applications processor for consumer and industrial products, rev. 9 6 freescale semiconductor 2features table 3 describes the digital and analog modules of the device. table 3. i.mx25 digital and analog modules block mnemonic block name subsystem brief description 1-wire 1-wire interface connectivity peripherals 1-wire support provided for interfacing with an on-board eeprom, and smart battery interfaces, for example: dallas ds2502. arm9 or arm926 arm926 platform and memory arm ? the arm926 platform consists of the arm926ej-s? core, the etm real-time debug modules, a 5x5 multi-layer ahb crossbar switch, and a ?primary ahb? complex. it contains the 16 kbyte l1 instruction cache, 16 kbyte l1 data cache, 32 kbyte rom and 128 kbyte ram. ata ata module connectivity peripherals the ata module is an at attachment host interface. its main use is to interface with ide hard disc drives and atapi optical disc drives. it interfaces with the ata device over a number of ata signals. audmux digital audio mux multimedia peripherals the audmux is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (ssis) and peripheral serial interfaces (audio codecs). the audmux has two sets of interfaces: internal ports to on-chip peripherals, and external ports to off-chip audio devices. data is routed by configuring the appropriate internal and external ports. ccm clock control module clocks this block generates all clocks for the imx25 system. the ccm also manages the arm926 platform's low-power modes (wait, stop, and doze) by disabling peripheral clocks appropriately for power conservation. cspi(3) configurable serial peripheral interface connectivity peripherals this module is a serial interface equipped with data fifos. each master/slave-configurable spi module is capable of interfacing to both serial port interface master and slave devices. the cspi ready (spi_rdy) and slave select (ss) control signals enable fast data communication with fewer software interrupts. dryice dryice module security dryice provides volatile key storage for point-of-sale (pos) terminals, and a trusted time source for digital rights management (drm) schemes. several tamper-detect circuits are also provided to support key erasure and time invalidation in the event of tampering. alarms and/or interrupts can also assert if tampering is detected. dryice also includes a real time clock (rtc) that can be used in secure and non-secure applications. emi external memory interface connectivity peripherals the external memory interface (emi) module provides access to external memory for the arm and other masters. it is composed of four main submodules: ? m3if provides arbitration between multiple masters requesting access to the external memory. ? enhanced sdram/lpddr memory controller (esdctl) interfaces to ddr2 and sdr interfaces. ? nand flash controller (nfc) provides an interface to nand flash memories. ? wireless external interface memory controller (weim) interfaces to nor flash and psram.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 7 epit(2) enhanced periodic interrupt timer timer peripherals each enhanced periodic interrupt timer (epit) is a 32-bit set-and-forget timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly. esai enhanced serial audio interface connectivity peripherals esai provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, spdif transceivers, and other dsps. the esai consists of independent transmitter and receiver sections, each section with its own clock generator. esdhc(2) enhanced multimedia card/ secure digital host controller connectivity peripherals the features of the esdhc module, when serving as host, include the following: ? conforms to the sd host controller standard specification version 2.0 ? compatible with the jedec mmc system specification version 4.2 ? compatible with the sd memory card specification version 2.0 ? compatible with the sdio specification version 1.2 ? designed to work with sd memory, minisd memory, sdio, minisdio, sd combo, mmc and mmc rs cards ? configurable to work in one of the following modes: ?sd/sdio 1-bit, 4-bit ?mmc 1-bit, 4-bit, 8-bit ? full-/high-speed mode ? host clock frequency variable between 32 khz and 52 mhz ? up to 200-mbps data transfer for sd/sdio cards using four parallel data lines ? up to 416-mbps data transfer for mmc cards using eight parallel data lines fec fast ethernet controller connectivity peripherals the ethernet media access controller (mac) is designed to support both 10- and 100-mbps ethernet networks compliant with ieee 802.3 ? standard. an external transceiver interface and transceiver function are required to complete the interface to the media flexcan(2) controller area network module connectivity peripherals the controller area network (can) protocol is primarily designed to be used as a vehicle serial data bus running at 1 mbps. gpio(4) general purpose i/o modules system control peripherals used for general purpose input/output to external ics. each gpio module supports 32 bits of i/o. gpt(4) general purpose timers timer peripherals each gpt is a 32-bit free-running or set-and-forget mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in set-and-forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. table 3. i.mx25 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx25 applications processor for consumer and industrial products, rev. 9 8 freescale semiconductor i 2 c(3) i 2 c module connectivity peripherals inter-ic communication (i 2 c) is an industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. i 2 c is suitable for applications requiring occasional communications over a short distance between many devices. the interface operates up to 100 kbps with maximum bus loading and timing. the i 2 c system is a true multiple-master bus, including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer. iim ic identification module security the iim provides the primary user-visible mechanism for interfacing with on-chip fuse elements. among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring a fixed value. iomux i/o multiplexer pins each i/o multiplexer provides a flexible, scalable multiplexing solution: ? up to eight output sources multiplexed per pin ? up to four destinations for each input pin ? unselected input paths are held at constant level for reduced power consumption kpp keypad port connectivity peripherals kpp can be used for either keypad matrix scanning or general purpose i/o. lcdc lcd controller multimedia peripherals lcdc provides display data for external gray-scale or color lcd panels. lcdc is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or cstn), and active-matrix color (active color or tft) lcd panels. max arm platform multilayer ahb crossbar switch arm platform max concurrently supports up to five simultaneous connections between master ports and slave ports. max allows for concurrent transactions to occur from any master port to any slave port. pwm(4) pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images. it can also generate tones. the pwm uses 16-bit resolution and a 4x16 data fifo to generate sound. sdma smart dma engine system control the sdma provides dma capabilities inside the processor. it is a shared module that implements 32 dma channels. sim(2) subscriber identity module interface connectivity peripherals the sim is an asynchronous interface designed to facilitate communication with sim cards or pre-paid phone cards. this module was designed based on the iso7816 standard; however, the module does require an external companion controller to allow communication to certain smart cards or to pass certain certifications, such as emv. the sim supports only 11 and 12etu cards and can communicate at the default rate, which is obtained at fi/di=372/1. an external companion controller is required to support cards aligned on 10.8 or 11.8etu and to support other rates, such as those obtained at fi/di=372/2 and fi/di=372/4. sjc secure jtag interface system control peripherals the system jtag controller (sjc) provides debug and test control with maximum security. table 3. i.mx25 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 9 2.1 special signal considerations special signal considerations are listed in table 4 . the package contact assignment is found in section 4, ?package information and contact assignment .? signal descriptions are provided in the reference manual. . slcd smart lcd controller multimedia peripherals the slcdc module transfers data from the display memory buffer to the external display device. spba shared peripheral bus arbiter system control the spba controls access to the shared peripherals. it supports shared peripheral ownership and access rights to an owned peripheral. ssi(2) i2s/ssi/ac97 interface connectivity peripherals the ssi is a full-duplex serial port that allows the processor to communicate with a variety of serial protocols, including the freescale semiconductor spi standard and the inter-ic sound bus standard (i2s). the ssis interface to the audmux for flexible audio routing. tsc (and adc) touchscreen controller (and a/d converter) multimedia peripherals the touchscreen controller and associated analog-to-digital converter (adc) together provide a resistive touchscreen solution. the module implements simultaneous touchscreen control and auxiliary adc operation for temperature, voltage, and other measurement functions. uart(5) uart interface connectivity peripherals each of the uart modules supports the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none) ? programmable baud rates up to 4 mhz. this is a higher maximum baud rate than the 1.875 mhz specified by the tia/eia-232-f standard and previous freescale uart modules. 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud ? irda-1.0 support (up to sir speed of 115200 bps) ? option to operate as 8-pins full uart, dce, or dte usbotg usbhost high-speed usb on-the-go connectivity peripherals the usb module provides high-performance usb on-the-go (otg) and host functionality (up to 480 mbps), compliant with the usb 2.0 specification, the otg supplement, and the ulpi 1.0 low pin count specification. the module has dma capab ilities for handling data transfer between internal buffers and system memory. an otg hs phy and host fs phy are also integrated. table 4. signal considerations signal description bat_vdd dryice backup power supply input. clk0 clock-out pin; renders the internal clock visible to users for debugging. the clock source is controllable through crm registers. this pin can also be configured (through muxing) to work as a normal gpio. clk_sel used to select the arm clock source from mpll out or from external ext_armclk. in normal operation, clk_sel should be connected to gnd. ext_armclk primarily for freescale factory use. there is no internal on-chip pull-up/down on this pin, so it must be externally connected to gnd or vdd. aside from factory use, this pin can also be configured (through muxing) to work as a normal gpio. table 3. i.mx25 digital and analog modules (continued) block mnemonic block name subsystem brief description
i.mx25 applications processor for consumer and industrial products, rev. 9 10 freescale semiconductor mesh_c, mesh_d wire-mesh tamper detect pins that can be routed at the pcb board to detect attempted tampering of a protected wire. when security measures are implemented, mesh_c should be pulled-up or connected to nvcc_dryice and triggers a tamper event when floating or when connected to mesh_d. mesh_d should be pulled-down or connected to gnd and triggers an event when floating or connected to mesh_c. these pins can be left unconnected if the dryice security features are not being used. nvcc_dryice this is the dryice power supply output. the supply source is qvdd when the i.mx25 is in run mode. when i.mx25 is in reduced power mode, the dryice supply source is the batt_vdd supply. this pin can be used to power external dryice components (external tamper detect, wire-mesh tamper detect). in order to guarantee the power-loss protection feature which guarantees that rtc and/or secure keys be maintained after power-off an external capacitor no less than 4 f must be connected to this supply output pin. a 4.7 f capacitor is recommended. osc_byp the 32 khz oscillator bypass-control pin. if this signal is pulled down, then osc32k_extal and osc32k_xtal analog pins should be tied to the external 32.768 khz crystal circuit. if on the other hand the signal is pulled up, then the external 32 khz oscillator output clock must be connected to osc32k_extal analog pin, and osc32k_xtal can be no connect (nc). osc32k_extal osc32k_xtal these analog pins are connected to an external 32 khz clk circuit depending on the state of osc_byp pin (see the description of osc_byp under the preceding bullet). the 32 khz reference clk is required for normal operation. power_fail an interrupt from pmic, which should be connected to a low-battery detection circuit. this signal is internally connected to an on-chip 100 k pull-down device. if there is no low-battery detection, then users can tie this pin to gnd through a pull-down resistor, or leave the signal as nc. this pin can also be configured to work as a normal gpio. ref external adc reference voltage. ref may be tied to gnd if the user plans to only use the internally generated 2.5 v reference supply. sjc_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ) is allowed, but the value should be much smaller than the on-chip 100 k pull-up. tamper_a, tamper _b dryice external tamper detect pins, active high. if tamper_a or tamper_b is connected to nvcc_dryice, then external tampering is detected. these pins can be left unconnected if the dryice security features are not being used. test_mode for freescale factory use only. this signal is internally connected to an on-chip pull-down device. users must either float this signal or tie it to gnd. upll_bypclk primarily for freescale factory use. there is no internal on-chip pull-up/down on this pin, so it must be externally connected to gnd or vdd. aside from factory use, this pin can also be configured (through muxing) to work as a normal gpio. usbphy1_rref determines the reference current for the usb phy1 bandgap reference. an external 10 k 1% resistor to gnd is required. usbphy2_dm usbphy2_dp the output impedance of these signals is expected at 10 . it is recommended to also have on-board 33 series resistors (close to the pins). table 4. signal considerations (continued) signal description
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 11 3 electrical characteristics this section provides the device-level and module-level electrical characteristics for the i.mx25. 3.1 i.mx25 chip-level conditions this section provides the chip-level electrical characteristics for the ic. 3.1.1 dc absolute maximum ratings table 5 provides the dc absolute maximum operating conditions. caution ? stresses beyond those listed under table 5 may cause permanent damage to the device. ? exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ? table 5 gives stress ratings only?functional operation of the device is not implied beyond the conditions indicated in table 6 . 3.1.2 dc operating conditions table 6 provides the dc recommended operating conditions. table 5. dc absolute maximum ratings parameter symbol min. max. units supply voltage qv dd ?0.5 1.52 v supply voltage (level shift i/o) v ddiomax ?0.5 3.6 v esd damage immunity: v esd v human body model (hbm) ? 2500 charge device model (cdm) ? 400 machine model (mm) ? 200 input voltage range v imax ?0.5 nv dd + 0.3 v storage temperature range t storage ?40 105 o c table 6. dc operating conditions parameter symbol min. typ. max. units core supply voltage (at 266 mhz) qv dd 1.15 1.34 1.52 v core supply voltage (at 400 mhz) qv dd 1.38 1.45 1.52 v coin battery 1 bat_vdd v dd_bat 1.15 ? 1.55 v i/o supply voltage, gpio nfc,csi,sdio nv dd_gpio1 1.75 ? 3.6 v
i.mx25 applications processor for consumer and industrial products, rev. 9 12 freescale semiconductor i/o supply voltage, gpio crm,lcdc,jtag,misc nv dd_gpio2 3.0 3.3 3.6 ? i/o supply voltage ddr (mobile ddr mode) emi1, emi2 nv dd_mddr 1.75 ? 1.95 v i/o supply voltage ddr (ddr2 mode) emi1,emi2 nv dd_ddr2 1.75 ? 1.9 v i/o supply voltage ddr (sdram mode) emi1,emi2 nv dd_sdram 1.75 ? 3.6 v supply of usbphy1 (hs) usbphy1_vdda_bias, usbphy1_upll_vdd,usbphy1_vdda v dd_usbphy1 3.17 3.3 3.43 v supply of usbphy2 (fs) usbphy2_vdd v dd_usbphy2 3.0 3.3 3.6 v supply of osc24m osc24m_vdd v dd_osc24m 3.0 3.3 3.6 v supply of pll mpll_vdd,upll_vdd v dd_pll 1.4 ? 1.65 v supply of touchscreen adc nvcc_adc v dd_tsc 3.0 3.3 3.6 v external reference of touchscreen adc ref vref 2.5 v dd_tsc v dd_tsc v fusebox program supply voltage fuse_vdd 2 fusev dd (program mode) 3.3 5% ? 3.6 v supply output 3 nvcc_dryice v dd_ 1.0 ? 1.55 v operating ambient temperature t a ?40 ? 85 o c 1 v dd_bat must always be powered by battery in security application. in non-security case, v dd_bat can be connected to qv dd . 2 the fusebox read supply is connected to supply of the full speed usbphy2_vdd. fuse_vdd is only used for programming. it is recommended that fuse_vdd be connected to ground when not being used for programming. see table 7 for current parameters. 3 nvcc_dryice is a supply output. an external capacitor no less than 4 f must be connected to it. a 4.7 f capacitor is recommended. table 6. dc operating conditions (continued) parameter symbol min. typ. max. units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 13 3.1.3 fusebox supply current parameters table 7 lists the fusebox supply current parameters. 3.1.4 interface frequency limits table 8 provides information for interface frequency limits. table 9 provides the recommended external crystal specifications. table 9. recommended external crystal specifications table 10 provides the recommended external reference clock oscillator specifications (when reference is used from an external clock source). table 10. recommended external reference clock specifications table 7. fusebox supply current parameters parameter symbol min. typ. max. units efuse program current 1 current to program one efuse bit the associated vdd_fuse supply = 3.6 v 1 the current i program is during program time (t program ). i program 26 35 62 ma efuse read current 2 current to read an 8-bit efuse word 2 the current i read is present for approximately 50 ns of the read access to the 8-bit word. i read ? 12.5 15 ma table 8. interface frequency limits parameter min. typ. max. units jtag: tck frequency of operation dc 5 10 mhz osc24m_xtal oscillator ? 24 ? mhz osc32k_xtal oscillator ? 32.768 ? khz 24 mhz 32.768 khz frequency tolerance <= 30 ppm <= 30 ppm esr < 80 50 k~60 k load capacitor 8 pf?12 pf 6 pf?8 pf (12 pf?16 pf on each pin) shunt capacitor < 7 pf 1 pf drive level > 150 w > 1 w 24 mhz 32.768 khz voh min = 0.7* vdd min = 0.7* vdd vol max = 0.3* vdd max = 0.3* vdd frequency tolerance = 30 ppm = 30 ppm trise 1% tclock 1% tclock
i.mx25 applications processor for consumer and industrial products, rev. 9 14 freescale semiconductor 3.1.5 usb_phy current consumption table 11 provides information for usb_phy current consumption. 3.1.6 power modes table 12 describes the core, clock, and module settings for the different power modes of the processor. tfall 1% tclock 1% tclock duty cycle 50% 50% table 11. usb phy current consumption 1 1 values must be verified parameter conditions typ. (@typ. temp) max. (@max. temp) unit analog supply usbphy1_vdda_bias, usbphy1_upll_vdd, usbphy1_vdda (3.3 v) full speed rx 11.4 ? ma tx 22,6 ? high speed rx 21.5 ? tx 33.8 ? suspend ? 0.6 a analog supply usbphy2_vdd (3.3 v) full speed rx 120 ? a tx 25 ? ma low speed rx 252 ? a tx 5.5 ? ma all supplies suspend 50 100 a table 12. i.mx25 power mode settings core/clock/module power mode doze wait stop/sleep 1 1 sleep mode differs from stop mode in that the core voltage is reduced to 1 v. run (266 mhz) run (400 mhz) arm core platform clock is off in wait-for-interrupt mode ? active @ 266 mhz active @ 400 mhz well bias on off on off off mcu pll on on off on on usb pll off off off on on osc24m on on off on on osc32k on on on on on other modules off off off on on
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 15 table 13 shows typical current consumption for the various power supplies under the various power modes. in the reduced power mode, shown in table 14 , the i.mx25 is powered down, while the rtc clock and the secure keys (in secure-use case), remain operati onal. bat_vdd is tied to a battery while all other supplies are turned off. note in this low-power mode, i.mx25 cannot be woken up with an interrupt; it must be powered back up before it can detect any events. table 13. i.mx25 power mode current consumption power group power supplies voltage setting current consumption for power modes 1 1 values are typical, under typical use conditions. doze wait stop sleep nvcc_emi nvcc_emi1 nvcc_emi2 3.0 v 5 a3.15 a3.51 a3.61 a nvcc_crm nvcc_crm 3.0 v 1.15 a4.31 ? 0.267 ? 0.32 ? nvcc_ other nvcc_sdio nvcc_csi nvcc_nfc nvcc_jtag nvcc_lcdc nvcc_misc 3.0 v 31.2 a29.5 ? 31.7 a32.1 ? nvcc_adc nvcc_adc 3.0 v 163 a3.25 ? 1.14 ? 0.871 ? osc24m osc24m_ vdd 3.0 v 906 a903 ? 10.2 ? ma 10.5 ? pll_vdd mpll_vdd upll_vdd 1.4 v 6.83 ma 6.83 m 38.9 ? 39.1 ? qvdd qvdd 1.15 v 8.79 ma 11.28 ma 842 a 665 a usbphy1_ vdda usbphy1_ vdda 3.17 v 240 a240 ? 241 ? 242 ? usbphy1_ vdda_vbias usbphy1_ vdda_vbias 3.17 v 0.6 ? 1.46 ? 0.328 ? 0.231 ? usbphy1_ upll_vdd usbphy1_ upll_vdd 3.17 v 201 ? 201 ? 191 ? 191 ? usbphy2 usbphy2_ vdd 3.0 v 158 a 0158 ? 164 ? 164 ? table 14. imx25 reduced power mode current consumption power group power supply voltage setting typical current consumption bat_vdd bat_vdd 1.15 v 9.95 a 1.55 v 12.6 a
i.mx25 applications processor for consumer and industrial products, rev. 9 16 freescale semiconductor 3.2 supply power-up/power-down requirements and restrictions any i.mx25 board design must comply with the power-up and power-down sequence guidelines given in this section to ensure reliable operation of the device. recommended power-up and power-down sequences are given in the following subsections. caution deviations from the guidelines in this section may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the i.mx25 (worst-case scenario) note for security applications, the coin battery must be connected during both power-up and power-down sequences to ensure that security keys are not unintentionally erased. 3.2.1 power-up sequence for those users that are not using dryice/srtc, the following power-up sequence is recommended: 1. assert power on reset (por). 2. turn on qvdd digital logic domain supplies. 3. turn on nvccx digital i/o power supplies after qvdd is stable. 4. turn on all other analog power supplies, including usbphy1_vdda_bias, usbphy1_upll_vdd, usbphy1_vdda, usbphy2_vdd, osc24m_vdd, mppll_vdd, upll_vdd, nvcc_adc, and fusevdd (fusevdd is tied to gnd if fuses are not programmed), after all nvccx digital i/o supplies are stable. 5. negate the por signal. note ? the user is advised to connect fusevdd to gnd except when fuses are programmed, to prevent unintentional blowing of fuses. ? other power-up sequences may be possible; however, the above sequence has been verified and is recommended. ? there is a 1 ms minimum time betw een supplies coming up, and a 1 ms minimum time between por_b assert and de-assert. ? the dv/dt should be no faster than 0.25 v/ s for all power supplies, to avoid triggering esd circuit.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 17 figure 2 shows the power-up sequence diagram. after por_b is asserted, core vdd and nvddx can be powered up. after core vdd and nvddx are stable, the analog supplies can be powered up. figure 2. power-up sequence diagram 3.2.2 power-down sequence there are no special requirements for the power-down sequence. all power supplies can be shut down at the same time. 3.2.3 srtc dryice power-up/down sequence in order to guarantee dryice power-loss protection, including retention of srtc time data during power down, users must do the following: ? place a proper capacitor on the nvcc_dryice output pin, and ? implement the below power-up/down sequence 1. assert power on reset (por). 2. turn on nvcc_crm. 3. turn on qvdd digital logic domain supplies for not less than 1 ms and not more than 32 ms, after nvcc_crm reaches 90% of 3.3 v. note this is to guarantee that por is stable already at nvcc_crm/qvdd power domain interface before qvdd is turned on, and por instantly propagates to qvdd domain after qvdd is turned on. 4. turn on other nvccx digital i/o power supplies for not less than 1 ms and not more than 32 ms, after qvdd reaches 90% of 1.2 v. 5. turn on all other analog power supplies, including usbphy1_vdda_bias, usbphy1_upll_vdd, usbphy1_vdda, usbphy2_vdd, nvcc_adc, osc24m_vdd, mppll_vdd, upll_vdd, and fusevdd (fusevdd is tied to gnd if fuses are not programmed) for not less than 1 ms and not more than 32 ms, after nvccx reaches 90% of 3.3 v.
i.mx25 applications processor for consumer and industrial products, rev. 9 18 freescale semiconductor note this is to guarantee that analog peripherals can get properly initialized (reset) values from q vdd domain and nvccx domain. 6. negate the por signal for at least 90 s after all previous steps. note ? this is to guarantee that both por logi c and clocks are stable inside the i.mx25 chip, before por is removed. ? the dv/dt should be no faster than 0.25 v/us for all power supplies, to avoid triggering esd circuit. in addition, the following powe r-down sequence is recommended: 1. turn off power for analog parts, including usbphy1_vdda_bias, usbphy1_upll_vdd, usbphy1_vdda, usbphy2_vdd, nvcc_adc, and fusevdd (fusevdd is tied to gnd if fuses are not programmed). 2. turn off qvdd. 3. turn off nvccx, pll, osc, and other powers. note the power-down steps can be executed simultaneously, or very shortly one after another. 3.3 power characteristics table 15 shows values representing maximum current numbers for the i.mx25 under worst case voltage and temperature conditions. these values are derived from the i.mx25 with core clock speed up to 400 mhz. additionally, no power saving techniques su ch as clock gating were implemented when measuring these values. common supplies are bundled according to the i.mx25 power-up sequence requirements. peak numbers are provided for system designers so that the i.mx25 power supply requirements are satisfied during startup and transi ent conditions. freescale recommends that system current measurements are taken with customer-specific use-cases to reflect the normal operating conditions in the end system. table 15. power consumption power supply voltage (v) max current (ma) qvdd 1.52 360 nvcc_emi1, nvcc_emi2 1.9 30 nvcc_crm, nvcc_sdio, nvcc_csi, nvcc_nfc, nvcc_jtag, nvcc_lcdc, nvcc_misc 3.6 110 mpll_vdd, upll_vdd 1.65 20 usbphy1_vdda_bias, usbphy1_upll_vdd, usbphy1_vdda, usbphy2_vdd, osc24m_vdd, nvcc_adc 3.3 40
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 19 the method for obtaining the maximum current is as follows: 1. measure the worst case power consumption on individual rails using directed test on i.mx25. 2. correlate the worst case power consumption power measurements with the worst case power consumption simulations. 3. combine common voltage rails based on the power supply sequencing requirements (add the worst case power consumption on each rail within some test cases from several test cases run, to maximize different rails in the power group). 4. guard the worst case numbers for temperature and process variation. 5. the sum of individual rails is greater than the real world power consumption, since a real system does not typically maximize the power cons umption on all periphe rals simultaneously. 6. batt_vdd current is measured when the system is in reduced power mode maintaining the rtc. when the system is in run mode, qvdd is used to supply the dryice, so this current becomes negligible. see table 12 , for more details on the power modes. note the values mentioned above should not be taken as a typical max run data for specific use cases. these values are absolute max data. freescale recommends that the system current measurements are taken with customer-specific use-cases to reflect normal operating conditions in the end system. 3.4 thermal characteristics the thermal resistance characteristics for the device are given in table 16 . these values are measured under the following conditions: ? two-layer substrate ? substrate solder mask thickness: 0.025 mm ? substrate metal thicknesses: 0.016 mm ? substrate core thickness: 0.200 mm ? core through i.d: 0.118 mm, core through plating 0.016 mm. ? flag: trace style with ground balls under the die connected to the flag ? die attach: 0.033 mm non-conducti ve die attach, k = 0.3 w/m k ? mold compound: generic mold compound; k = 0.9 w/m k fuse_vdd 1 3.6 62 batt_vdd 1.55 0.030 1 the fuse_vdd rail is connected to ground. it only needs a voltage if the system fuse burning is needed. table 15. power consumption (continued) power supply voltage (v) max current (ma)
i.mx25 applications processor for consumer and industrial products, rev. 9 20 freescale semiconductor 3.5 i/o dc parameters this section includes the dc parameters of the following i/o types: ? ddr i/o: mobile ddr (mddr), double data rate (ddr2), or synchronous dynamic random access memory (sdram) ? general purpose i/o (gpio) note the term ?ovdd? in this section refers to the associated supply rail of an input or output. the association is shown in the ?signal multiplexing? chapter of the reference manual. 3.5.1 ddr i/o dc parameters the ddr pad type is configured by the iomuxc_sw_pad_ctl_grp_ddrtype register (see the external signals and pin multiplexing chapter of the i.mx25 reference manual for details). table 16. thermal resistance data rating condition symbol value unit junction to ambient 1 natural convection 1 junction-to-ambient thermal resistance determined per jedc jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board (1s) r eja 55 c/w junction to ambient 1 natural convection four layer board (2s2p) r eja 33 c/w junction to ambient 1 (@200 ft/min) single layer board (1s) r ejma 46 c/w junction to ambient 1 (@200 ft/min) four layer board (2s2p) r ejma 29 c/w junction to boards 2 2 junction-to-board thermal resistance determined per jedc jesd51-8. thermal test board meets jedec specification for this package. ?r ejb 22 c/w junction to case (top) 3 3 junction-to-case at the top of the package determined using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. ?r ejctop 13 c/w junction to package top 4 4 thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per jedec jesd51-2. when greek letters are not available, this thermal characterization parameter is written as psi-jt. natural convection jt 2c/w
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 21 3.5.1.1 ddr_type = 00 standard setting ddr i/o dc parameters table 17 shows the i/o parameters for mobile ddr. these settings are suitable for mddr and ddr2 1.8v ( 5%) applications. 3.5.1.2 ddr_type = 01 sdram i/o dc parameters table 18 shows the dc i/o parameters for sdram. table 17. mobile ddr i/o dc electrical characteristics dc electrical characteristics symbol test conditions min. typ. max. units high-level output voltage voh i oh = ?1ma i oh = specified drive ovdd ? 0.08 0.8 ovdd ?? v low-level output voltage vol i ol = 1ma i ol = specified drive ??0.08 0.2 ovdd v high-level output current i ioh voh = 0.8 ovddv standard drive high drive max. drive ?3.6 ?7.2 ?10.8 ?? ma low-level output current i iol vol = 0.2 ovddv standard drive high drive max. drive 3.6 7.2 10.8 ?? ma high-level dc cmos input voltage vih ? 0.7 ovdd ovdd ovdd+0.3 v low-level dc cmos input voltage vil ? ?0.3 0 0.3 ovdd v differential receiver vth+ vth+ ? ? 100 mv differential receiver vth- vth- ?100 ? ? mv input current (no pull-up/down) iin vi = 0 vi = ovdd ??110 60 na high-impedance i/o supply current icc-ovdd vi = ovdd or 0 ? ? 990 na high-impedance core supply current icc-vddi vi = vdd or 0 ? ? 1220 na table 18. sdram dc electrical characteristics dc electrical characteristics symbol test conditions min. typ. max. units high-level output voltage voh ioh = specified drive (ioh = ?4, ?8, ?12, ?16ma) 2.4 ? ? v low-level output voltage vol ioh = specified drive (ioh = 4, 8, 12, 16ma) ??0.4v high-level output current i ioh standard drive high drive max. drive ?4.0 ?8.0 ?12.0 ??ma low-level output current i iol standard drive high drive max. drive 4.0 8.0 12.0 ??ma high-level dc input voltage vih ? 2.0 ? 3.6 v
i.mx25 applications processor for consumer and industrial products, rev. 9 22 freescale semiconductor 3.5.1.3 ddr_type = 10 max setting ddr i/o dc parameters table 19 shows the i/o parameters for ddr2 (sstl_18). low-level dc input voltage vil ? ?0.3 v ? 0.8 v input current (no pull-up/down) iin vi = 0 vi = ovdd ??150 80 na high-impedance i/o supply current icc-ovdd vi = ovdd or 0 ? ? 1180 na high-impedance core supply current icc-vddi vi = vdd or 0 ? ? 1220 na table 19. ddr2 (sstl_18) i/o dc electrical characteristics dc electrical characteristics symbol test conditions min. typ. max. units high-level output voltage voh ? ovdd ? 0.28 ? ? v low-level output voltage vol ? ? ? 0.28 v output min. source current 1 1 ovdd = 1.7 v; v out = 1.42 v. (v out -ovdd)/ioh must be less than 21 w for values of v out between ovdd and ovdd-0.28 v. iioh ? ?13.4 ? ? ma output min. sink current 2 2 ovdd = 1.7 v; v out = 280 mv. v out /iol must be less than 21 w for values of v out between 0 v and 280 mv. simulation circuit for parameters v oh and v ol for i/o cells is below. iiol ? 13.4 ? ? ma dc input logic high vih(dc) ? ovdd/2 + 0.125 ? ovdd + 0.3 v dc input logic low vil(dc) ? ?0.3 v ? ovdd/2 ? 0.125 v dc input signal voltage 3 (for differential signal) 3 vin(dc) specifies the allowable dc excursion of each differential input. vin(dc) ? ?0.3 ? ovdd + 0.3 v dc differential input voltage 4 4 vid(dc) specifies the input differential voltage required for switching. the minimum value is equal to vih(dc) - vil(dc). vid(dc) ? 0.25 ? ovdd+0.6 v termination voltage 5 5 vtt is expected to track ovdd/2. vtt ? ovdd/2 ? 0.04 ovdd/2 ovdd/2 + 0.04 input current 6 (no pull-up/down) 6 minimum condition: bcs model, 1.95 v, and ?40 c. typical condition: typical model, 1.8 v, and 25 c. maximum condition: wcs model, 1.65 v, and 105 c. iin vi = 0 vi = ovdd ? ? 110 60 na high-impedance i/o supply current 6 icc-ovdd vi = ovdd or 0 ? ? 980 na high-impedance core supply current 6 icc-vddi vi = vdd or 0 ? ? 1210 na table 18. sdram dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min. typ. max. units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 23 3.5.2 gpio i/o dc parameters table 20 shows the i/o parameters for gpio. table 20. gpio dc electrical characteristics dc electrical characteristics symbol test conditions min. typ. max. units high-level output voltage 1 voh ioh=?1ma ioh = specified drive ovdd ? 0.15 0.8 ovdd ??v low-level output voltage 1 vol iol=1m a iol=specified drive ? ? 0.15 0.2 ovdd v high-level output current for slow mode i ioh voh=0.8 ovdd standard drive high drive max. drive ?2.0 ?4.0 ?8.0 ??ma high-level output current for fast mode i ioh voh=0.8 ovdd standard drive high drive max. drive ?4.0 ?6.0 ?8.0 ??ma low-level output current for slow mode i iol voh=0.2 ovdd standard drive high drive max. drive 2.0 4.0 8.0 ??ma low-level output current for fast mode i iol voh=0.2 ovdd standard drive high drive max. drive 4.0 6.0 8.0 ??ma high-level dc input voltage vih ? 0.7 ovdd ? ovdd v low-level dc input voltage vil ? ?0.3 v ? 0.3 ovdd v input hysteresis vhys ovdd = 3.3 v ovdd = 1.8v 370 290 ? 420 320 mv schmitt trigger vt+ 1 vt+ ? 0.5 ovdd ? ? v schmitt trigger vt? 1 vt? ? ? ? 0.5 ovdd v pull-up resistor (22 k pu) rpu vi=0 18.5 22 25.6 k pull-up resistor (47 k pu) rpu vi=0 41 47 55 k pull-up resistor (100 k pu) rpu vi=0 85 100 120 k pull-down resistor (100 k pd) rpd vi = ovdd 85 100 120 k input current (no pull-up/down) iin vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v ? ? 100 60 77 50 na input current (22 k pu) iin vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v 117 0.0001 64 0.0001 ? 184 0.0001 104 0.0001 a
i.mx25 applications processor for consumer and industrial products, rev. 9 24 freescale semiconductor 3.6 ac electrical characteristics this section provides the ac parameters for slow and fast i/o. figure 3 shows the load circuit for output. figure 4 through figure 6 show the output transition time and propagation waveforms. figure 3. load circuit for output figure 4. output pad transition time waveform input current (47 k pu) iin vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v 54 0.0001 30 0.0001 ?88 0.0001 49 0.0001 a input current (100 k pu) iin vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v 25 0.0001 14 0.0001 ?42 0.0001 23 0.0001 a input current (100 k pd) iin vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v 25 0.0001 14 0.0001 ?42 0.001 23 0.0001 a high-impedance i/o supply current icc?ovdd vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v ? ? 688 688 560 560 na high-impedance core supply current icc?vddi vi = 0, ovdd = 3.3 v vi = ovdd = 3.3 v vi = 0, ovdd = 1.8 v vi = ovdd = 1.8 v ? ? 490 490 410 410 na 1 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. table 20. gpio dc electrical characteristics (continued) dc electrical characteristics symbol test conditions min. typ. max. units tes t poi nt from output under test cl cl includes package, probe and jig capacitance 0v ovdd 20% 80% 80% 20% pa 1 pa1 output (at pad)
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 25 figure 5. output pad propagation and transition time waveform figure 6. output enable to output valid tphl tplh 0v ovdd 50% 50% 50% 20% 80% 80% 20% ttlh tthl output (at pad) input from core 0v vdd 50% (1 ns transition times) vdd 50% 50% signal open from core tpv ovdd output (at pad) signal ?1? pdat from core signal ?0? pdat from core vdd 0
i.mx25 applications processor for consumer and industrial products, rev. 9 26 freescale semiconductor 3.6.1 slow i/o ac parameters table 21 shows the slow i/o ac parameters. table 21. slow i/o ac parameters parameter symbol test voltage test capacitance min. rise/fall typ. rise/fall max. rise/fall units duty cycle fduty ? ? 40 ? 60 % output pad transition times 1 (max. drive) tpr 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 0.95/0.84 1.58/1.37 2.70/2.50 3.40/3.20 1.36/1.11 2.19/1.77 1.80/1.40 2.80/2.14 2.06/1.60 3.20/2.47 3.01/2.37 4.63/3.38 ns output pad transition times 1 (high drive) tpr 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 1.60/1.39 2.94/2.51 1.85/1.48 2.93/2.37 2.23/1.79 4.05/3.17 2.90/2.17 4.56/3.40 3.26/2.50 5.72/4.27 4.75/3.43 7.33/5.26 output pad transition times 1 (standard drive) tpr 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 3.07/2.62 5.82/4.95 3.04/2.47 5.37/4.40 4.22/3.30 7.94/6.19 4.73/3.50 7.70/8.10 6.03/4.48 11.28/8.28 3.01/2.36 4.63/3.38 output pad propagation delay 1 (max. drive), 50%?50% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 1.92/2.1 2.44/2.53 2.05/2.27 2.71/2.84 2.96/2.96 3.7/3.64 3.32/3.67 4.39/4.51 4.47/4.38 5.54/5.31 5.27/5.85 7.00/7.15 ns output pad propagation delay 1 (high drive), 50%?50% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.35/2.49 3.31/3.43 2.58/2.69 3.62/3.60 3.58/3.61 4.9/4.786 4.17/4.27 5.86/5.61 5.35/5.24 7.19/6.8 6.64/6.74 9.34/8.76 output pad propagation delay 1 (standard drive), 50%?50% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 3.39/3.51 5.28/5.35 3.71/3.68 5.52/5.32 5.03/4.89 7.6/7.14 6.03/5.75 8.80/7.96 7.39/6.95 10.97/9.45 9.64/8.97 13.9/11.3 output pad propagation delay 1 (max. drive), 40%?60% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 1.942/2.04 2.378/2.48 2.03/2.28 2.59/2.73 2.923/2.95 3.541/3.53 3.19/3.59 4.10/4.33 4.33/4.3 5.29/5.09 4.97/5.64 6.43/6.77 ns output pad propagation delay 1 (high drive), 40%?60% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.29/2.44 3.05/3.20 2.45/2.62 3.36/3.39 3.42/3.49 4.46/4.45 3.86/4.07 5.34/5.22 5.05/5.02 6.53/6.3 6.02/6.35 8.40/8.08 output pad propagation delay 1 (standard drive), 40%?60% tpo 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 3.12/3.26 4.60/4.73 3.43/3.46 4.89/4.79 4.58/4.53 6.61/6.32 5.48/5.34 7.75/7.16 6.69/6.42 9.5/8.32 8.65/8.26 12.2/9.97
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 27 output enable to output valid delay 1 (max. drive), 50%?50% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.13/2.01 2.65/2.46 2.31/2.45 2.95/3.01 3.3/3.045 4.038/3.639 3.76/4.00 4.81/4.82 5.072/4.609 6.142/5.423 6.11/6.47 7.81/7.73 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.56/2.43 3.55/3.21 2.85/2.90 3.87/3.78 3.91/3.604 5.21/4.598 4.65/4.64 6.31/5.95 5.937/5.36 7.776/6.694 7.58/7.44 10.3/9.43 output enable to output valid delay 1 (standard drive), 50%?50% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 3.60/3.28 5.50/4.81 4.04/3.94 5.85/5.56 5.35/4.70 7.93/6.603 6.65/6.21 9.47/8.49 7.97/6.836 11.58/9.338 10.9/9.22 15.5/13.3 output enable to output valid delay 1 (max. drive), 40%?60% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.152/1.7 2.6/2.07 2.28/2.46 2.83/2.93 3.25/2.68 3.88/3.17 3.62/3.92 4.50/4.62 4.93/4.162 5.842/4.846 5.77/6.24 7.20/7.32 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 2.497/2.036 3.254/2.647 2.71/2.81 3.59/3.56 3.75/3.135 4.8/3.9 4.31/4.23 5.75/5.54 5.633/4.782 7.117/5.84 6.89/7.01 9.23/8.71 output enable to output valid delay 1 (standard drive), 40%?60% tpv 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 3.326/2.7 4.81/3.85 3.73/3.69 5.16/4.99 4.9/3.9 6.9/5.4 6.04/5.77 8.28/7.61 7.269/5.95 10.12/7.86 9.81/9.11 13.4/11.8 output pad slew rate 2 (max. drive) tps 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 0.79/1.12 0.49/0.73 0.30/0.42 0.20/0.29 1.30/1.77 0.84/1.23 0.54/0.73 0.35/0.50 2.02/2.58 1.19/1.58 0.91/1.20 0.60/0.80 v/ns output pad slew rate 2 (high drive) tps 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 0.48/0.72 0.27/0.42 0.19/0.28 0.12/0.18 0.76/1.10 0.41/0.62 0.34/0.49 0.34/0.49 1.17/1.56 0.63/0.86 0.58/0/79 0.36/0.49 output pad slew rate 2 (standard drive) tps 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 0.25/0.40 0.14/0.21 0.12/0.18 0.07/0.11 0.40/0.59 0.21/0.32 0.20/0.30 0.11/0.17 0.60/0.83 0.32/0.44 0.34/0.47 0.20/0.27 table 21. slow i/o ac parameters (continued) parameter symbol test voltage test capacitance min. rise/fall typ. rise/fall max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 28 freescale semiconductor output pad di/dt 3 (max. drive) tdit 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 15 16 7 7 36 38 21 22 76 80 56 58 ma /ns output pad di/dt 3 (high drive) tdit 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 8 9 5 5 20 21 14 15 45 47 38 40 output pad di/dt 3 (standard drive) tdit 3.0?3.6 v 3.0?3.6 v 1.65?1.95 v 1.65?1.95 v 25 pf 50 pf 25 pf 50 pf 4 4 2 2 10 10 7 7 22 23 18 19 input pad propagation delay without hysteresis, 50%?50% 4 tpi ? 1.6 pf 0.82/0.47 0.74/1 1.1/0.76 1.1/1.5 1.6/1.04 1.75/2.16 ns input pad propagation delay with hysteresis, 50%?50% 4 tpi ? 1.6 pf 1.1/1.3 1.75/1.63 1.43/1.6 2.67/2.22 2/2 2.92/3 input pad propagation delay without hysteresis, 40%?60% 4 tpi ? 1.6 pf 1.62/1.28 1.82/1.55 1.9/1.56 2.28/1.87 2.38/1.82 2.95/2.54 input pad propagation delay with hysteresis, 40%?60% 4 tpi ? 1.6 pf 1.88/2.1 2.4/2.6 2.2/2.4 3/3.07 2.7/2.75 3.77/3.71 input pad transition times without hysteresis 4 trfi ? 1.6 pf 0.16/0.12 0.23/0.18 0.33/0.29 input pad transition times with hysteresis 4 trfi 1.6 pf 0.16/0.13 0.22/0.18 0.33/0.29 maximum input transition times 5 trm ? ? ? ? 25 ns 1 maximum condition for tpr, tpo, and tpv: wcs model, 1.1 v, i/o 3.0 v (3.0?3.6 v range) or 1.65 v (1.65?1.95 v range), and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 3.6 v (3.0?3.6 v range) or 1.95 v (1.65?1.95 v range), and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 3.0 v (3.0?3.6 v range) or 1.65 v (1.65?1.95 v range), and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 3.6 v (3.0?3.6 v range) or 1.95 v (1.65?1.95 v range), and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 3.0 v (3.0?3.6 v range) or 1.65 v (1.65?1.95 v range), and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 3.6 v or 1.95 v (1.65?1.95 v range), and ?40 c. input transition time from pad is 5 ns (20%?80%). 5 hysteresis mode is recommended for input with transition time greater than 25 ns. table 21. slow i/o ac parameters (continued) parameter symbol test voltage test capacitance min. rise/fall typ. rise/fall max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 29 3.6.2 fast i/o ac parameters table 22 shows the fast i/o ac parameters for ovdd = 1.65?1.95 v. table 22. fast i/o ac parameters for ovdd = 1.65 ? 1.95 v parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 ? 60 % output pad transition times 1 (max. drive) tpr 25 pf 50 pf 0.88/0.77 1.45/1.24 1.36/1.10 2.20/1.80 2.10/1.70 3.50/2.70 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.10/0.92 1.84/1.54 1.65/1.33 2.80/2.20 2.64/2.10 4.40/3.30 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 1.60/1.35 2.74/2.26 2.47/1.95 4.20/3.20 3.99/3.10 6.56/4.86 ns output pad propagation delay 1 (max. drive), 50%?50% tpo 25 pf 50 pf 1.64/1.53 2.15/2.01 2.68/2.41 3.47/3.08 4.25/3.74 5.50/4.77 ns output pad propagation delay 1 (high drive), 50%?50% tpo 25 pf 50 pf 1.82/1.71 2.46/2.29 2.98/2.66 3.96/3.49 4.74/4.13 6.27/5.37 ns output pad propagation delay 1 (standard drive), 50%?50% tpo 25 pf 50 pf 2.24/2.06 3.17/2.92 3.63/3.15 5.09/4.41 5.73/4.84 8.06/6.75 ns output pad propagation delay 1 (max. drive), 40%?60% tpo 25 pf 50 pf 1.67/1.58 2.09/1.98 2.63/2.38 3.30/2.97 4.06/3.63 5.14/4.51 ns output pad propagation delay 1 (high drive), 40%?60% tpo 25 pf 50 pf 1.94/1.73 2.34/2.22 2.89/2.61 3.69/3.30 4.49/3.97 5.76/5.01 ns output pad propagation delay 1 (standard drive), 40%?60% tpo 25 pf 50 pf 2.15/1.99 2.94/2.74 3.39/2.99 4.65/4.07 5.28/4.53 7.28/6.13 ns output enable to output valid delay 1 (max. drive), 50%?50% tpv 25 pf 50 pf 1.87/1.70 2.36/2.16 3.06/2.71 3.83/3.37 4.97/4.30 6.18/5.30 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 25 pf 50 pf 2.05/1.88 2.68/2.45 3.67/2.98 4.32/3.78 5.46/4.72 6.98/5.92 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 25 pf 50 pf 2.49/2.25 3.40/3.08 4.06/3.50 5.50/4.73 6.57/5.49 8.88/7.37 ns output enable to output valid delay 1 (max. drive), 40%?60% tpv 25 pf 50 pf 1.90/1.74 2.30/2.13 3.00/2.69 3.65/3.24 4.76/4.18 5.79/5.02 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 25 pf 50 pf 2.06/1.90 2.56/2.37 3.28/2.33 4.04/3.59 5.21/4.54 6.43/5.54 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 25 pf 50 pf 2.39/2.18 3.16/2.89 3.80/3.18 5.03/4.37 6.05/5.14 8.02/6.72 ns output pad slew rate 2 (max. drive) tps 25 pf 50 pf 0.40/0.57 0.25/0.36 0.72/0.97 0.43/0.61 1.2/1.5 0.72/0.95 v/ns output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.38/0.48 0.20/0.30 0.59/0.81 0.34/0.50 0.98/1.27 0.56/0.72 v/ns output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.23/0.32 0.13/0.20 0.40/0.55 0.23/0.34 0.66/0.87 0.38/0.52 v/ns
i.mx25 applications processor for consumer and industrial products, rev. 9 30 freescale semiconductor table 23 shows the fast i/o ac parameters for ovdd = 3.0?3.6 v. output pad di/dt 3 (max. drive) tdit 25 pf 50 pf 7 7 43 46 112 118 ma/ns output pad di/dt 3 (high drive) tdit 25 pf 50 pf 11 12 31 33 81 85 ma/ns output pad di/dt 3 (standard drive) tdit 25 pf 50 pf 9 10 27 28 71 74 ma/ns input pad propagation delay without hysteresis, 50%?50% 4 tpi 1.6 pf 0.74/1 1.1/1.5 1.75/2.16 ns input pad propagation delay with hysteresis, 50%?50% 4 tpi 1.6 pf 1.75/1.63 2.67/2.22 2.92/3 ns input pad propagation delay without hysteresis, 40%?60% 4 tpi 1.6 pf 1.82/1.55 2.28/1.87 2.95/2.54 ns input pad propagation delay with hysteresis, 40%?60% 4 tpi 1.6 pf 2.4/2.6 3/3.07 3.77/3.71 ns input pad transition times without hysteresis 4 trfi 1.6 pf 0.16/0.12 0.30/0.18 0.33/0.29 ns input pad transition times with hysteresis 4 trfi 1.6 pf 0.16/0.13 0.30/0.18 0.33/0.29 ns maximum input transition times 5 trm ? ? ? 25 ns 1 maximum condition for tpr, tpo, and tpv: wcs model, 1.1 v, i/o 1.65 v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 1.95 v, and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 1.65 v and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 1.95 v and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 1.65 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 1.95 v and ?40 c. input transition time from pad is 5 ns (20%?80%). 5 hysteresis mode is recommended for input with transition time greater than 25 ns. table 23. fast i/o ac parameters for ovdd = 3.0 ? 3.6 v parameter symbol test condition min. rise/fall typ. max. rise/fall units duty cycle fduty 40 60 % output pad transition times 1 (max drive) tpr 25 pf 50 pf 0.80/0.70 1.40/1.60 1.12/2.51 1.60/2.39 1.64/1.32 2.84/2.10 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.00/0.90 1.95/1.66 1.43/1.16 2.66/2.09 2.05/1.60 3.70/2.80 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 1.50/1.30 2.90/2.50 2.09/1.67 3.40/3.09 3.00/2.30 5.56/4.12 ns output pad propagation delay 1 (max drive), 50%?50% tpo 25 pf 50 pf 1.20/1.28 1.67/1.75 1.74/1.73 2.39/2.32 2.67/2.52 3.58/3.33 ns table 22. fast i/o ac parameters for ovdd = 1.65 ? 1.95 v (continued) parameter symbol test condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 31 output pad propagation delay 1 (high drive), 50%?50% tpo 25 pf 50 pf 1.35/1.42 1.98/2.04 1.95/1.91 2.81/2.68 2.96/2.76 4.16/3.78 ns output pad propagation delay 1 (standard drive), 50%?50% tpo 25 pf 50 pf 1.77/1.85 2.70/2.78 2.54/2.48 3.82/3.62 3.80/3.60 5.62/5.10 ns output pad propagation delay 1 (max drive), 40%?60% tpo 25 pf 50 pf 1.37/1.50 1.74/1.88 1.94/2.05 2.46/2.55 2.95/3.07 3.71/3.75 ns output pad propagation delay 1 (high drive), 40%?60% tpo 25 pf 50 pf 1.48/1.61 1.98/2.10 2.11/2.19 2.78/2.81 3.19/3.26 4.14/4.09 ns output pad propagation delay 1 (standard drive), 40%?60% tpo 25 pf 50 pf 1.84/1.97 2.58/2.71 2.61/2.67 3.62/3.58 3.95/3.95 5.36/5.15 ns output enable to output valid delay 1 (max drive), 50%?50% tpv 25 pf 50 pf 1.34/1.32 1.81/1.79 1.91/1.81 2.56/2.40 2.92/2.67 3.83/3.47 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 25 pf 50 pf 1.48/1.47 2.12/2.1 2.12/2.00 2.98/2.76 3.21/2.92 4.41/3.94 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 25 pf 50 pf 1.90/1.90 2.85/2.83 2.70/2.60 4.00/3.70 4.07/3.74 5.86/5.24 ns output enable to output valid delay 1 (max drive), 40%?60% tpv 25 pf 50 pf 1.55/1.42 1.93/1.81 2.25/2.08 2.77/2.58 3.50/3.31 4.24/3.99 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 25 pf 50 pf 1.67/1.54 2.16/2.03 2.41/2.23 3.08/2.86 3.74/3.51 4.66/4.34 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 25 pf 50 pf 2.02/1.90 2.76/2.63 2.91/2.71 3.91/3.62 4.48/4.21 5.85/5.39 ns output pad slew rate 2 (max drive) tps 25 pf 50 pf 0.96/1.40 0.54/0.83 1.54/2.10 0.85/1.24 2.30/3.00 1.26/1.70 v/ns output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.76/1.10 0.41/0.64 1.19/1.71 0.63/0.95 1.78/2.39 0.95/1.30 v/ns output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.52/0.78 0.28/0.44 0.80/1.19 0.43/0.64 1.20/1.60 0.63/0.87 v/ns output pad di/dt 3 (max drive) didt 25 pf 50 pf 46 49 108 113 250 262 ma/ns output pad di/dt 3 (high drive) didt 25 pf 50 pf 35 37 82 86 197 207 ma/ns output pad di/dt 3 (standard drive) didt 25 pf 50 pf 22 23 52 55 116 121 ma/ns input pad propagation delay without hysteresis, 50%?50% 4 tpi 1.6pf 0.729/0.458 0.97/0.0649 1.404/0.97 ns input pad propagation delay with hysteresis, 50%?50% 4 tpi 1.6pf 1.203/0.938 1.172/1.187 1.713/1.535 ns input pad propagation delay without hysteresis, 40%?60% 4 tpi 1.6pf 0.879/0.977 1.434/1.12 1.854/1.427 ns table 23. fast i/o ac parameters for ovdd = 3.0 ? 3.6 v (continued)
i.mx25 applications processor for consumer and industrial products, rev. 9 32 freescale semiconductor 3.6.3 ddr i/o ac parameters the ddr pad type is configured by the iomuxc_sw_pad_ctl_grp_ddrtype register (see chapter 4, ?external signals and pin multiplexing,? in the i.mx25 multimedia applications processor reference manual ). 3.6.3.1 ddr_type = 00 standard setting i/o ac parameters and requirements table 24 shows ac parameters for mobile ddr i/o. these settings are suitable for mddr and ddr2 1.8v ( 5%) applications. input pad propagation delay with hysteresis, 40%?60% 4 tpi 1.6pf 1.353/1.457 1.637/1.659 2.163/1.991 ns input pad transition times without hysteresis 4 trfi 1.6pf 0.16/0.12 0.23/0.18 0.33/0.29 ns input pad transition times with hysteresis 4 trfi 1.6pf 0.16/0.13 0.22/0.18 0.33/0.29 ns maximum input transition times 5 trm ? ? ? ? ns 1 maximum condition for tpr, tpo, and tpv: wcs model, 1.1 v, io 3.0 v and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, io 3.6 v and ?40 c. input transition time from core is 1ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, io 3.0 v and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, io 3.6 v and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, io 3.0 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v , io 3.6 v and ?40 c. input transition time from pad is 5 ns (20%?80%). 5 hysteresis mode is recommended for input with transition time greater than 25 ns. table 24. ac parameters for mobile ddr i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency 1 f ? ? ? 133 mhz output pad transition times 1 (max. drive) tpr 25 pf 50 pf 0.52/0.51 0.98/0.96 0.79/0.72 1.49/1.34 1.25/1.09 2.31/1.98 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.13/1.10 2.15/2.10 1.74/1.55 3.28/2.92 2.71/2.30 5.11/4.31 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 2.26/2.19 4.30/4.18 3.46/3.07 6.59/5.79 5.39/4.56 10.13/8.55 ns output pad propagation delay 1 (max. drive), 50%?50% tpo 15 pf 35 pf 0.80/1.03 1.06/1.32 1.36/1.50 1.76/1.90 2.21/2.40 2.83/2.82 ns output pad propagation delay 1 (high drive), 50%?50% tpo 15 pf 35 pf 1.04/1.27 1.63/1.90 1.74/1.83 2.63/2.69 2.79/2.70 4.18/3.86 ns output pad propagation delay 1 (standard drive), 50%?50% tpo 15 pf 35 pf 1.55/1.80 2.72/3.06 2.53/2.57 4.31/4.29 4.03/3.76 6.80/6.19 ns output pad propagation delay 1 (max. drive), 40%?60% tpo 15 pf 35 pf 0.80/0.91 1.06/1.12 1.44/1.59 1.76/1.91 2.24/2.29 2.74/2.75 ns table 23. fast i/o ac parameters for ovdd = 3.0 ? 3.6 v (continued)
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 33 output pad propagation delay 1 (high drive), 40%?60% tpo 15 pf 35 pf 1.04/1.09 1.63/1.56 1.73/1.83 2.43/2.52 2.69/2.62 3.79/3.62 ns output pad propagation delay 1 (standard drive), 40%?60% tpo 15 pf 35 pf 1.50/1.74 2.73/2.42 2.36/2.41 3.77/3.78 3.67/3.46 5.86/5.37 ns output enable to output valid delay 1 (max. drive), 50%?50% tpv 15 pf 35 pf 1.17/1.01 1.43/1.30 1.93/1.61 2.33/2.00 3.06/2.55 3.69/3.13 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 15 pf 35 pf 1.38/1.28 1.97/1.92 2.25/1.99 3.16/2.86 3.58/3.10 5.01/4.39 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 15 pf 35 pf 1.92/1.57 3.12/3.16 3.11/2.79 4.97/4.59 4.98/4.13 7.97/6.98 ns output enable to output valid delay 1 (max. drive), 40%?60% tpv 15 pf 35 pf 1.28/1.12 1.49/1.36 2.01/1.70 2.33/2.01 3.09/2.60 3.60/3.06 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 15 pf 35 pf 1.43/1.33 1.90/1.84 2.24/1.99 2.96/2.68 3.47/3.02 4.59/4.03 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 15 pf 35 pf 1.85/1.78 2.80/2.81 2.91/2.62 4.37/4.53 4.54/3.96 6.88/6.05 ns output pad slew rate 2 (max. drive) tps 25 pf 50 pf 0.80/0.92 0.43/0.50 1.35/1.50 0.72/0.81 2.23/2.27 1.66/1.68 v/ns output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.37/0.43 0.19/0.23 0.62/0.70 0.33/0.37 1.03/1.05 0.75/0.77 v/ns output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.18/0.22 0.10/0.12 0.31/0.35 0.16/0.18 0.51/0.53 0.38/0.39 v/ns output pad di/dt 3 (max. drive) tdit 25 pf 50 pf 64 69 171 183 407 432 ma/ns output pad di/dt 3 (high drive) tdit 25 pf 50 pf 37 39 100 106 232 246 ma/ns output pad di/dt 3 (standard drive) tdit 25 pf 50 pf 18 20 50 52 116 123 ma/ns input pad transition times 4 trfi 1.0 pf 0.07/0.08 0.11/0.13 0.16/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.77/1.00 1.22/1.45 1.89/2.21 ns input pad propagation delay, 40%?60% 4 tpi 1.0 pf 1.59/1.82 2.04/2.27 2.69/3.01 ns 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 1.65 v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 1.95 v and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 1.65 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 1.95 v, and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 1.65 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 1.95 v and ?40 c. input transition time from pad is 5 ns (20%?80%). table 24. ac parameters for mobile ddr i/o (continued) parameter symbol load condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 34 freescale semiconductor table 25 shows the ac parameters for mobile ddr pbijtov18_33_ddr_clk i/o. table 25. ac parameters for mobile ddr pbijtov18_33_ddr_clk i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency 1 f ? ? ? 133 mhz output pad transition times 1 (max. drive) tpr 25 pf 50 pf 0.52/0.51 0.98/0.96 0.79/0.72 1.49/1.34 1.25/1.09 2.31/1.98 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.13/1.10 2.15/2.10 1.74/1.55 3.28/2.92 2.71/2.30 5.11/4.31 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 2.26/2.19 4.30/4.18 3.46/3.07 6.59/5.79 5.39/4.56 10.13/8.55 ns output pad propagation delay 1 (max. drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 1.28/1.19 1.56/1.47 1.97/1.83 2.37/2.23 2.98/2.78 3.57/3.37 ns output pad propagation delay 1 (high drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 1.54/1.43 2.14/2.04 2.34/2.20 3.22/3.08 3.54/3.33 4.85/4.65 ns output pad propagation delay 1 (standard drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 2.05/1.94 3.27/3.16 3.11/2.96 4.86/4.72 4.70/4.50 7.33/7.12 ns output pad propagation delay 1 (max. drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 1.45/1.36 1.73/1.64 2.13/2.00 2.53/2.40 3.14/2.94 3.74/3.54 ns output pad propagation delay 1 (high drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 1.70/1.60 2.31/2.21 2.51/2.37 3.38/3.24 3.70/3.50 5.02/4.82 ns output pad propagation delay 1 (standard drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 2.22/2.11 3.43/3.32 3.27/3.13 5.02/4.88 4.87/4.66 7.49/7.29 ns output enable to output valid delay 1 (max. drive), 50%?50% tpv 15 pf 35 pf 1.16/1.12 1.42/1.41 1.91/1.81 2.31/2.20 3.10/2.89 3.72/3.47 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 15 pf 35 pf 1.39/1.39 1.98/2.02 2.28/2.18 3.18/3.04 3.69/3.43 5.08/4.69 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 15 pf 35 pf 1.90/1.94 3.07/3.20 3.09/2.94 4.88/4.66 4.95/4.55 7.73/7.05 ns output enable to output valid delay 1 (max. drive), 40%?60% tpv 15 pf 35 pf 1.28/1.24 1.49/1.47 2.00/1.90 2.32/2.21 3.14/2.93 3.64/3.41 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 15 pf 35 pf 1.45/1.44 1.92/1.95 2.28/2.19 2.99/2.87 3.60/3.36 4.69/4.36 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 15 pf 35 pf 1.85/1.88 2.78/2.88 2.92/2.79 4.34/4.16 4.5894.25 6.79/6.24 ns output pad slew rate 2 (max. drive) tps 25 pf 50 pf 0.37/0.45 0.30/0.36 0.64/0.79 0.52/0.61 1.14/1.36 0.90/1.02 v/ns
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 35 table 26 shows the ac requirements for mobile ddr i/o. output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.30/0.37 0.21/0.25 0.51/0.63 0.36/0.42 091/1.06 0.63/0.67 v/ns output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.22/0.26 0.13/0.16 0.37/0.44 0.23/0.26 0.65/0.72 0.39/0.40 v/ns output pad di/dt 3 (max. drive) tdit 25 pf 50 pf 65 70 171 183 426 450 ma/ns output pad di/dt 3 (high drive) tdit 25 pf 50 pf 31 33 82 87 233 245 ma/ns output pad di/dt 3 (standard drive) tdit 25 pf 50 pf 16 17 43 46 115 120 ma/ns input pad transition times 4 trfi 1.0 pf 0.07/0.08 0.11/0.13 0.16/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.84/0.84 1.40/1.34 2.25/2.16 ns input pad propagation delay, 40%?60% 4 tpi 1.0 pf 1.66/1.66 2.22/2.16 3.06/2.97 ns 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 1.65 v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 1.95 v and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 1.65 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 1.95 v, and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 1.65 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 1.95 v and ?40 c. input transition time from pad is 5 ns (20%?80%). table 26. ac requirements for mobile ddr i/o parameter symbol min. max. units ac input logic high vih(ac) 0.8 ovdd ovdd+0.3 v ac input logic low vil(ac) ?0.3 0.2 ovdd v ac differential input voltage vid(ac) 0.6 ovdd ovdd+0.6 v ac differential cross point voltage for input vix(ac) 0.4 ovdd ovdd+0.6 v table 25. ac parameters for mobile ddr pbijtov18_33_ddr_clk i/o (continued) parameter symbol load condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 36 freescale semiconductor 3.6.3.2 ddr_type = 01 sdram i/o ac parameters and requirements table 27 shows ac parameters for sdram i/o. table 27. ac parameters for sdram i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency 1 f ? ? ? 133 mhz output pad transition times 1 (max. drive) tpr 25 pf 50 pf 0.82/0.87 1.56/1.67 1.14/1.13 2.13/2.09 1.62/1.50 3.015/2.7 7 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.23/1.31 2.31/2.47 1.71/1.68 3.22/3.12 2.39/2.22 4.53/4.16 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 2.44/2.60 4.65/4.99 3.38/3.27 6.38/6.23 4.73/4.38 9.05/8.23 ns output pad propagation delay 1 (max. drive), 50%?50% tpo 15 pf 35 pf 0.97/1.19 2.85/3.21 1.69/0.75 2.02/2.30 2.17/2.46 2.93/3.27 ns output pad propagation delay 1 (high drive), 50%?50% tpo 15 pf 35 pf 1.15/1.39 3.57/3.91 1.72/1.93 2.54/2.85 2.51/2.77 3.66/3.97 ns output pad propagation delay 1 (standard drive), 50%?50% tpo 15 pf 35 pf 2.01/1.57 5.73/6.05 2.45/2.69 4.10/4.51 3.54/3.77 5.84/6.13 ns output pad propagation delay 1 (max. drive), 40%?60% tpo 15 pf 35 pf 1.06/1.26 1.38/1.38 1.53/1.73 1.96/2.23 2.18/2.47 2.78/3.12 ns output pad propagation delay 1 (high drive), 40%?60% tpo 15 pf 35 pf 1.15/1.20 1.75/1.67 1.72/1.93 2.37/2.66 2.45/2.71 3.35/3.67 ns output pad propagation delay 1 (standard drive), 40%?60% tpo 15 pf 35 pf 1.91/2.01 2.88/2.56 2.30/2.52 3.59/3.97 3.26/3.50 5.06/5.36 ns output enable to output valid delay 1 (max. drive), 50%?50% tpv 15 pf 35 pf 0.90/1.27 1.07/1.77 1.44/1.89 1.66/2.51 2.19/2.87 2.51/3.69 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 15 pf 35 pf 1.01/1.48 1.37/2.33 1.58/2.16 2.06/3.09 2.38/3.23 3.06/4.46 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 15 pf 35 pf 1.32/2.14 2.04/3.67 2.02/3.00 3.00/4.91 3.01/4.36 4.40/6.90 ns output enable to output valid delay 1 (max. drive), 40%?60% tpv 15 pf 35 pf 1.03/1.34 1.16/1.74 1.54/1.94 1.74/2.44 2.26/2.88 2.55/3.54 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 15 pf 35 pf 1.11/1.51 1.39/2.10 1.65/2.15 2.03/2.89 2.43/3.16 2.95/4.13 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 15 pf 35 pf 1.35/2.03 1.91/3.23 1.99/2.83 2.76/4.30 2.89/4.03 3.98/6.01 ns output pad slew rate 2 (max. drive) tps 25 pf 50 pf 1.11/1.20 0.97/0.65 1.74/1.75 0.92/0.94 2.42/2.46 1.39/1.30 v/ns output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.76/0.80 0.40/0.43 1.16/1.19 0.61/0.63 1.76/1.66 0.93/0.87 v/ns
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 37 table 28 shows ac parameters for sdram pbijtov18_33_ddr_clk i/o. output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.38/0.41 0.20/0.22 0.59/0.60 0.31/0.32 0.89/0.82 0.47/0.43 v/ns output pad di/dt 3 (max. drive) tdit 25 pf 50 pf 89 94 198 209 398 421 ma/ns output pad di/dt 3 (high drive) tdit 25 pf 50 pf 59 62 132 139 265 279 ma/ns output pad di/dt 3 (standard drive) tdit 25 pf 50 pf 29 31 65 69 132 139 ma/ns input pad transition times 4 trfi 1.0 pf 0.07/0.08 0.11/0.12 0.16/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.35/1.17 0.63/1.53 1.16/2.04 ns input pad propagation delay, 40%?60% 4 tpi ? 1.18/1.99 1.45/2.35 1.97/2.85 ? 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 3.0 v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 3.6 v and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 3.0 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 3.6 v, and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 3.0 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 3.6 v and ?40 c. input transition time from pad is 5 ns (20%?80%). table 28. ac parameters for sdram pbijtov18_33_ddr_clk i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency 1 f ? ? ? 133 mhz output pad transition times 1 (max. drive) tpr 25 pf 50 pf 0.82/0.87 1.56/1.67 1.14/1.13 2.13/2.09 1.62/1.50 3.015/2.7 7 ns output pad transition times 1 (high drive) tpr 25 pf 50 pf 1.23/1.31 2.31/2.47 1.71/1.68 3.22/3.12 2.39/2.22 4.53/4.16 ns output pad transition times 1 (standard drive) tpr 25 pf 50 pf 2.44/2.60 4.65/4.99 3.38/3.27 6.38/6.23 4.73/4.38 9.05/8.23 ns output pad propagation delay 1 (max. drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 1.50/1.40 1.95/1.85 2.23/2.07 2.81/2.66 3.28/3.04 4.06/3.82 ns output pad propagation delay 1 (high drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 1.69/1.59 2.35/2.25 2.48/2.32 3.35/3.19 3.63/3.38 4.80/4.56 ns output pad propagation delay 1 (standard drive), 50%?50% input signals and crossing of output signals tpo 15 pf 35 pf 2.26/2.15 3.59/3.49 3.24/3.08 4.98/4.82 4.66/4.42 7.00/6.75 ns output pad propagation delay 1 (max. drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 1.67/1.57 2.11/2.02 2.39/2.24 2.97/2.82 3.45/3.21 4.23/3.99 ns table 27. ac parameters for sdram i/o (continued) parameter symbol load condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 38 freescale semiconductor output pad propagation delay 1 (high drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 1.85/1.75 2.52/2.42 2.65/2.49 3.51/3.36 3.79/3.55 4.97/4.72 ns output pad propagation delay 1 (standard drive), 40%?60% input signals and crossing of output signals tpo 15 pf 35 pf 2.42/2.32 3.76/3.66 3.40/3.25 5.15/4.99 4.83/4.59 7.17/6.92 ns output enable to output valid delay 1 (max. drive), 50%?50% tpv 15 pf 35 pf 1.37/1.34 1.77/1.83 2.22/2.02 2.77/2.63 3.53/3.12 4.30/3.92 ns output enable to output valid delay 1 (high drive), 50%?50% tpv 15 pf 35 pf 1.55/1.56 2.15/2.29 2.46/2.30 3.28/3.21 3.87/3.47 5.02/4.67 ns output enable to output valid delay 1 (standard drive), 50%?50% tpv 15 pf 35 pf 2.07/2.18 3.28/3.65 3.20/3.08 4.84/4.90 4.92/4.50 7.21/6.89 ns output enable to output valid delay 1 (max. drive), 40%?60% tpv 15 pf 35 pf 1.46/1.42 1.77/1.81 2.28/2.07 2.71/2.56 3.54/3.13 4.15/3.78 ns output enable to output valid delay 1 (high drive), 40%?60% tpv 15 pf 35 pf 1.60/1.59 2.07/2.18 2.47/2.30 3.12/3.02 3.82/3.41 4.72/4.37 ns output enable to output valid delay 1 (standard drive), 40%?60% tpv 15 pf 35 pf 2.01/2.09 2.96/3.26 3.05/2.91 4.34/4.37 4.64/4.23 6.45/6.13 ns output pad slew rate 2 (max. drive) tps 25 pf 50 pf 1.11/1.20 0.60/0.65 1.74/1.75 0.93/0.95 2.63/2.48 1.39/1.29 v/ns output pad slew rate 2 (high drive) tps 25 pf 50 pf 0.75/0.81 0.40/0.43 1.16/1.18 0.62/0.64 1.76/1.65 094/0.87 v/ns output pad slew rate 2 (standard drive) tps 25 pf 50 pf 0.38/0.41 0.20/0.22 0.59/0.61 0.31/0.32 0.89/0.83 0.47/0.43 v/ns output pad di/dt 3 (max. drive) tdit 25 pf 50 pf 89 95 202 213 435 456 ma/ns output pad di/dt 3 (high drive) tdit 25 pf 50 pf 60 63 135 142 288 302 ma/ns output pad di/dt 3 (standard drive) tdit 25 pf 50 pf 29 31 67 70 144 150 ma/ns input pad transition times 4 trfi 1.0 pf 0.07/0.08 0.11/0.12 0.16/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.56/0.69 0.87/1.08 1.37/1.62 ns input pad propagation delay, 40%?60% 4 tpi 1.38/1.51 1.68/1.89 2.18/2.42 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 3.0 v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 3.6 v and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 3.0 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 3.6 v, and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 3.0 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 3.6 v and ?40 c. input transition time from pad is 5 ns (20%?80%). table 28. ac parameters for sdram pbijtov18_33_ddr_clk i/o (continued) parameter symbol load condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 39 3.6.3.3 ddr_type = 10 max setting i/o ac parameters and requirements table 29 shows ac parameters for ddr2 i/o. table 30 shows ac parameters for ddr2 pbijtov18_33_ddr_clk i/o. table 29. ac parameters for ddr2 i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? ? 133 mhz output pad transition times 1 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 1. v, and 105 c. minimum condition for tpr, tpo, and tpv: bcs model, 1.3 v, i/o 1.9 v and ?40 c. input transition time from core is 1 ns (20%?80%). tpr 25 pf 50 pf 0.53/0.52 1.01/0.98 0.80/0.72 1.49/1.34 1.19/1.04 2.21/1.90 ns output pad propagation delay, 50%?50% 1 tpo 25 pf 50 pf 0.93/1.25 1.26/1.54 1.56/1.70 2.07/2.19 2.52/2.53 3.29/3.24 ns output pad propagation delay, 40%?60% 1 tpo 25 pf 50 pf 1.01/1.17 1.27/1.53 1.60/1.75 2.00/2.14 2.49/2.52 3.11/3.10 ns output enable to output valid delay, 50%?50% 1 tpv 25 pf 50 pf 1.30/1.19 1.62/1.54 2.17/1.81 2.56/2.29 3.35/2.84 3.35/2.54 ns output enable to output valid delay, 40%?60% 1 tpv 25 pf 50 pf 1.39/1.27 1.64/1.55 2.13/1.86 2.62/2.23 3.38/2.83 4.14/2.38 ns output pad slew rate 2 2 minimum condition for tps: wcs model, 1.1 v, i/o 1.7 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for fa lling edge. tps 25 pf 50 pf 0.86/0.98 0.46/054 1.35/1.5 0.72/0.81 2.15/2.19 1.12/1.16 v/ns output pad di/dt 3 3 maximum condition for tdit: bcs model, 1.3 v, i/o 1.9 v, and ?40 c. tdit 25 pf 50 pf 65 70 157 167 373 396 ma/ns input pad transition times 4 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 1.7 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v , i/o 1.9 v and ?40 c. input transition time from pad is 5 ns (20%?80%). trfi 1.0 pf 0.07/0.08 0.10/0.12 0.17/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.83/0.99 1.23/1.49 1.79/2.04 ns input pad propagation delay, 40%?60% 4 tpi 1.0 pf 1.65/1.81 2.05/2.31 2.60/2.84 ns table 30. ac parameters for ddr2 pbijtov18_33_ddr_clk i/o parameter symbol load condition min. rise/fall typ. max. rise/fall units duty cycle fduty ? 40 50 60 % clock frequency f ? ? ? 133 mhz output pad transition times 1 tpr 25 pf 50 pf 0.53/0.52 1.01/0.98 0.80/0.72 1.49/1.34 1.19/1.04 2.21/1.90 ns output pad propagation delay 1 , 50%?50% input signals and crossing of output signals tpo 25 pf 50 pf 1.3/1.21 1.59/1.5 1.97/1.84 2.37/2.24 2.91/2.71 3.48/3.28 ns
i.mx25 applications processor for consumer and industrial products, rev. 9 40 freescale semiconductor table 31 shows the ac requirements for ddr2 i/o. output pad propagation delay 1 , 40%?60% input signals and crossing of output signals tpo 25 pf 50 pf 1.47/1.38 1.75/1.67 2.13/2.00 2.54/2.40 3.072/2.87 3.65/3.45 ns output enable to output valid delay, 50%?50% 1 tpv 25 pf 50 pf 1.32/1.28 1.66/1.65 2.11/2.00 2.61/2.50 3.31/3.12 4.06/3.81 ns output enable to output valid delay, 40%?60% 1 tpv 25 pf 50 pf 1.40/1.37 1.67/1.66 2.16/2.06 2.56/2.45 3.30/3.13 3.89/3.67 ns output pad slew rate 2 tps 25 pf 50 pf 0.86/0.98 0.46/054 1.35/1.5 0.72/0.81 2.15/2.19 1.12/1.16 v/ns output pad di/dt 3 tdit 25 pf 50 pf 72 77 172 183 400 422 ma/ns input pad transition times 4 trfi 1.0 pf 0.07/0.08 0.10/0.12 0.17/0.20 ns input pad propagation delay, 50%?50% 4 tpi 1.0 pf 0.89/0.87 1.41/1.37 2.16/2.07 ns input pad propagation delay, 40%?60% 4 tpi 1.0 pf 1.71/1.69 2.22/2.18 2.98/2.88 ns 1 maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 v, i/o 1. v, and 105 c. minimum condition for tpr, tpo, and tpv: bc s model, 1.3 v, i/o 1.9 v and ?40 c. input transition time from core is 1 ns (20%?80%). 2 minimum condition for tps: wcs model, 1.1 v, i/o 1.7 v, and 105 c. tps is measured between vil to vih for rising edge and between vih to vil for falling edge. 3 maximum condition for tdit: bcs model, 1.3 v, i/o 1.9 v, and ?40 c. 4 maximum condition for tpi and trfi: wcs model, 1.1 v, i/o 1.7 v and 105 c. minimum condition for tpi and trfi: bcs model, 1.3 v, i/o 1.9 v and ?40 c. input transition time from pad is 5 ns (20%?80%). table 31. ac requirements for ddr2 i/o parameter 1 1 the jedec sstl_18 specification (jesd8-15a) for an sstl interface for class ii operation supersedes any specification in this document. symbol min. max. units ac input logic high vih(ac) ovdd/2 + 0.25 ovdd + 0.3 v ac input logic low vil(ac) ?0.3 ovdd/2 ? 0.25 v ac differential input voltage 2 2 vid(ac) specifies the input differential voltage |vtr?vcp| required for switching, where vtr is the ?true? input signal and vcp is the ?complementary? input signal. the minimum value is equal to vih(ac)?vil(ac) vid(ac) 0.5 ovdd + 0.6 v ac differential cross point voltage for input 3 3 the typical value of vix(ac) is expected to be about 0.5 ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) ovdd/2?0.175 ovdd/2 + 0.175 v ac differential cross point voltage for output 4 4 the typical value of vox(ac) is expected to be about 0.5 ovdd and vox(ac) is expected to track variation in ovdd. vox(ac) indicates the voltage at which differential output signal must cross. cload = 25 pf. vox(ac) ovdd/2?0.125 ovdd/2 + 0.125 v table 30. ac parameters for ddr2 pbijtov18_33_ddr_clk i/o (continued) parameter symbol load condition min. rise/fall typ. max. rise/fall units
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 41 3.7 module timing and electrical parameters this section contains the timing and el ectrical parameters for i.mx25 modules. 3.7.1 1-wire timing parameters figure 7 shows the reset and presence pulses (rpp) timing for 1-wire. figure 7. 1-wire rpp timing diagram table 32 lists the rpp timing parameters. figure 8 shows write 0 sequence timing, and table 33 describes the timing parameters (ow5?ow6) that are shown in the figure. figure 8. write 0 sequence timing diagram table 32. rpp sequence delay comparisons timing parameters id parameters symbol min. typ. max. units ow1 reset time low t rstl 480 511 ? s ow2 presence detect high t pdh 15 ? 60 s ow3 presence detect low t pdl 60 ? 240 s ow4 reset time high t rsth 480 512 ? s table 33. wr0 sequence timing parameters id parameter symbol min. typ. max. units ow5 write 0 low time t wr0_low 60 100 120 s ow6 transmission time slot t slot ow5 117 120 s 1-wire bus 1-wire memory device ?presence pulse? (owire_line) 1-wire tx ?reset pulse? ow1 ow2 ow3 ow4 ow5 ow6 1-wire bus (owire_line)
i.mx25 applications processor for consumer and industrial products, rev. 9 42 freescale semiconductor figure 9 and figure 10 show write 1 and read sequence timing, respectively. table 34 describes the timing parameters (ow7?ow8) that are shown in the figure. figure 9. write 1 sequence timing diagram figure 10. read sequence timing diagram table 34. wr1 /rd timing parameters id parameter symbol min. typ. max. units ow7 write 1 / read low time t low1 1515 s ow8 transmission time slot t slot 60 117 120 s ow9 release time t release 15 ? 45 s ow7 ow8 1-wire bus (owire_line) ow7 ow8 ow9 1-wire bus (owire_line)
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 43 3.7.2 ata timing parameters table 35 shows parameters used to specify the ata timing. these parameters depend on the implementation of the ata interface on silicon, the bus buffer used, the cable delay and cable skew. table 35. timing parameters name description value/contributing factor t bus clock period peripheral clock frequency ti_ds set-up time ata_data to ata_iordy edge (udma-in only) udma0 udma1 udma2,udma3 udma4 udma5 15 ns 10 ns 7ns 5ns 4ns ti_dh hold time ata_iordy edge to ata_data (udma-in only) udma0,udma1,udma2,udma3,udma4 udma5 5.0 ns 4.6 ns tco propagation delay bus clock l-to-h to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en 12.0 ns tsu set-up time ata_data to bus clock l-to-h 8.5 ns tsui set-up time ata_iordy to bus clock h-to-l 8.5 ns thi hold time ata_iordy to bus clock h-to-l 2.5 ns tskew1 maximum difference in propagation delay bus clock l-to-h to any of the following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en 7ns tskew2 maximum difference in buffer propagation delay for any of the following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en transceiver tskew3 maximum difference in buffer propagation delay for any of the following signals ata_iordy, ata_data (read) transceiver tbuf maximum buffer propagation delay transceiver tcable1 cable propagation delay for ata_data cable tcable2 cable propagation delay for control signals ata_dior , ata_diow , ata_iordy , ata_dmack cable tskew4 maximum difference in cable propagation delay between ata_iordy and ata_data (read) cable tskew5 maximum difference in cable propagation delay between ( ata_dior , ata_diow , ata_dmack ) and ata_cs0 , ata_cs1 , ata_da2 , ata_da1 , ata_da0 , ata_data (write) cable tskew6 maximum difference in cable propagation delay without accounting for ground bounce cable
i.mx25 applications processor for consumer and industrial products, rev. 9 44 freescale semiconductor 3.7.2.1 pio mode timing parameters figure 11 shows a timing diagram for pio read mode. figure 11. pio read mode timing to meet pio read mode timing requirements, a number of timing parameters must be controlled. table 36 shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions. table 36. timing parameters for pio read mode ata parameter pio read mode timing parameter 1 1 see figure 11 . relation adjustable parameter t1 t1 t1(min.) = time_1 t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2r t2(min.) = time_2r t ? (tskew1 + tskew2 + tskew5) time_2r t9 t9 t9(min.) = time_9 t ? (tskew1 + tskew2 + tskew6) time_9 t5 t5 t5(min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase time_2 t6 t6 0 ? ta ta ta(min.) = (1.5 + time_ax) t ? (tco + tsui + tcable2 + tcable2 + 2 tbuf) time_ax trd trd1 trd1(max.) = (?trd) + (tskew3 + tskew4) trd1(min.) = (time_pio_rdx ? 0.5) t ? (tsu + thi) (time_pio_rdx ? 0.5) t > tsu + thi + tskew3 + tskew4 time_pio_rdx t0 ? t0(min.) = (time_1 + time_2 + time_9) t time_1, time_2r, time_9 addr (see note 1) dior read data(15:0) iordy iordy t1 t2r t9 ta t5 t6 trd1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 45 figure 12 gives timing waveforms for pio write mode. figure 12. pio write mode timing to meet pio write mode timing requirements, a number of timing parameters must be controlled. table 37 shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions. table 37. timing parameters for pio write mode ata parameter pio write mode timing parameter 1 1 see figure 12 . relation adjustable parameter(s) t1 t1 t1(min.) = time_1 t ? (tskew1 + tskew2 + tskew5) time_1 t2 t2w t2(min.) = time_2w t ? (tskew1 + tskew2 + tskew5) time_2w t9 t9 t9(min.) = time_9 t ? (tskew1 + tskew2 + tskew6) time_9 t3 ? t3(min.) = (time_2w ? time_on) t ? (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4 t4 t4(min.) = time_4 t ? tskew1 time_4 ta ta ta = (1.5 + time_ax) t ? (tco + tsui + tcable2 + tcable2 + 2 tbuf) time_ax t0 ? t0(min.) = (time_1 + time_2 + time_9) t time_1, time_2r, time_9 ? ? avoid bus contention when switching buffer on by making ton long enough ? ? ? avoid bus contention when switching buffer off by making toff long enough ? addr (see note 1) diow write data(15:0) iordy iordy t1 t2w t9 ta buffer_en ton t4 toff tb dior t1
i.mx25 applications processor for consumer and industrial products, rev. 9 46 freescale semiconductor 3.7.2.2 multiword dma (mdma) mode timing figure 13 and figure 14 show the timing for mdma read and write modes, respectively. figure 13. mdma read mode timing figure 14. mdma write mode timing addr (see note 1) dior read data(15:0) dmarq dmack tm td tk tkjn tgr tfr tk1 te addr (see note 1) diow write data(15:0) dmarq dmack tkjn tk1 buffer_en tm ton td1 tk td toff
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 47 to meet timing requirements, a number of timing parameters must be controlled. see table 38 for details on timing parameters for mdma read and write modes. 3.7.2.3 ultra dma (udma) mode timing udma mode timing is more complicated than pio mode or mdma mode. in this section, timing diagrams for udma in- and out-transfers are provided. table 38. timing parameters for mdma read and write modes ata parameter mdma read 1 and write 2 timing parameters 1 see figure 13 . 2 see figure 14 . relation adjustable parameter(s) tm, ti tm tm(min.) = ti(min.) = time_m t ? (tskew1 + tskew2 + tskew5) time_m td td, td1 td1(min.) = td(min.) = time_d t ? (tskew1 + tskew2 + tskew6) time_d tk tk tk(min.) = time_k t ? (tskew1 + tskew2 + tskew6) time_k t0 ? t0(min.) = (time_d + time_k) t time_d, time_k tg(read) tgr tgr(min.?read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min.?drive) = td ? te(drive) time_d tf(read) tfr tfr(min.?drive) =0 k ? tg(write) ? tg(min.?write) = time_d t ?(tskew1 + tskew2 + tskew5) time_d tf(write) ? tf(min.?write) = time_k t ? (tskew1 + tskew2 + tskew6) time_k tl ? tl(max.) = (time_d + time_k?2) t ? (tsu + tco + 2 tbuf + 2 tcable2) time_d, time_k 3 3 tk1 in the udma figures equals (tk ?2 t). tn, tj tkjn tn= tj= tkjn = (max.(time_k,. time_jn) t ? (tskew1 + tskew2 + tskew6) time_jn ?ton toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ?
i.mx25 applications processor for consumer and industrial products, rev. 9 48 freescale semiconductor 3.7.2.3.1 udma in-transfer timing figure 15 shows the timing for udma in-transfer start. figure 15. timing for udma in-transfer start figure 16 shows the timing for host-terminated udma in-transfer. figure 16. timing for host-terminated udma in-transfer dmarq addr dior diow iordy data read dmack tack tenv tds tdh tc1 tc1 dmarq addr dior diow iordy data read dmack tds tdh tc1 tc1 data write buffer_en tack trp tx1 tzah tzah ton tdzfs tcvh toff tmli tmli
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 49 figure 17 shows timing for device-terminated udma in-transfer. figure 17. timing for device-terminated udma transfer timing parameters for udma in-burst are listed in table 39 . table 39. timing parameters for udma in-burst ata parameter spec. parameter value required conditions tack tack tack(min.) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv(min.) = (time_env t) ? (tskew1 + tskew2) tenv(max.) = (time_env t) + (tskew1 + tskew2) time_env tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough tdh tdh1 tdh ? (tskew3) ?ti_dh > 0 tcyc tc1 (tcyc ? tskew) > t t big enough trp trp trp(min.) = time_rp t ? (tskew1 + tskew2 + tskew6) time_rp ?tx1 1 1 there is a special timing requirement in the ata host that requires the internal diow to go only high three clocks after the la st active edge on the dstrobe signal. the equation given on this line tries to capture this constraint. make t on and t off big enough to avoid bus contention. (time_rp t) ? (tco + tsu + 3t + 2 tbuf + 2 tcable2) > trfs (drive) time_rp tmli tmli1 tmli1(min.) = (time_mlix + 0.4) t time_mlix tzah tzah tzah(min.) = (time_zah + 0.4) t time_zah tdzfs tdzfs tdzfs = (time_dzfs t) ? (tskew1 + tskew2) time_dzfs tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ? dmarq addr dior diow iordy data read dmack tds tdh tc1 tc1 data write buffer_en tack tss1 tzah ton tdzfs tcvh toff tzah tmli tmli tli5
i.mx25 applications processor for consumer and industrial products, rev. 9 50 freescale semiconductor 3.7.2.4 udma out-transfer timing figure 18 shows the timing for start of udma out-transfer. figure 18. timing for udma out-transfer start figure 19 shows timing for host-terminated udma out-transfer. figure 19. timing for host-terminated udma out-transfer dmarq addr diow dior iordy data write dmack tack tenv buffer_en ton tdzfs tdvs tdvh tdvs tcyc tcyc trfs1 tli1 dmarq addr diow dior dmack data write buffer_en tack tcvh toff tss tcyc iordy tli2 tli3 tdzfs_mli tcyc1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 51 timing parameters for udma out-bursts are listed in table 40 . 3.7.3 digital audio mux (audmux) timing the audmux provides a programmable interconnect logi c for voice, audio, and data routing between internal serial interfaces (ssi and sap) and external serial interfaces (audio and voice codecs). the ac timing of audmux external pins is governed by the ssi modules. for more information, see section 3.7.17, ?synchronous serial interface (ssi) timing .? 3.7.4 cmos sensor interface (csi) timing the csi enables the chip to connect directly to exte rnal cmos image sensors, which are classified as dumb or smart as follows: ? dumb sensors only support traditional sensor timing (vertical sync (vsync) and horizontal sync (hsync)) and output-only ba yer and statistics data. ? smart sensors support ccir656 video decoder form ats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats). the following subsections describe the csi timing in gated and ungated clock modes. table 40. timing parameters udma out-bursts ata parameter spec parameter value how to meet? tack tack tack(min.) = (time_ack t) ? (tskew1 + tskew2) time_ack tenv tenv tenv(min.) = (time_env t) ? (tskew1 + tskew2) tenv(max.) = (time_env t) + (tskew1 + tskew2) time_env tdvs tdvs tdvs = (time_dvs t) ? (tskew1 + tskew2) time_dvs tdvh tdvh tdvs = (time_dvh t) ? (tskew1 + tskew2) time_dvh tcyc tcyc tcyc = time_cyc t ? (tskew1 + tskew2) time_cyc t2cyc ? t2cyc = time_cyc 2 t time_cyc trfs1 trfs trfs = 1.6 t + tsui + tco + tbuf + tbuf ? ? tdzfs tdzfs = time_dzfs t ? (tskew1) time_dzfs tss tss tss = time_ss t ? (tskew1 + tskew2) time_ss tmli tdzfs_mli tdzfs_mli =max.(time_dzfs, time_mli) t ? (tskew1 + tskew2) ? tli tli1 tli1 > 0 ? tli tli2 tli2 > 0 ? tli tli3 tli3 > 0 ? tcvh tcvh tcvh = (time_cvh t) ? (tskew1 + tskew2) time_cvh ?ton toff ton = time_on t ? tskew1 toff = time_off t ? tskew1 ?
i.mx25 applications processor for consumer and industrial products, rev. 9 52 freescale semiconductor 3.7.4.1 gated clock mode timing figure 20 and figure 21 shows the gated clock mode timings for csi, and table 41 describes the timing parameters (p1?p7) shown in the figures. a frame starts with a rising/falling edge on vsync, then hsync is asserted and holds for the entire line. the pixel clock is valid as long as hsync is asserted. figure 20. csi gated clock mode?sensor data at falling edge, latch data at rising edge figure 21. csi gated clock mode?sensor data at rising edge, latch data at falling edge pixclk vsync data[15:0] p5 p1 p3 p4 hsync p2 p6 p7 pixclk vsync data[15:0] p6 p1 p3 p4 hsync p2 p5 p7
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 53 3.7.4.2 ungated clock mode timing figure 22 shows the ungated clock mode timings of csi, and table 42 describes the timing parameters (p1?p6) that are shown in the figure. in ungated mode the vsync and pixclk signals are used, and the hsync signal is ignored. figure 22. csi ungated clock mode?sensor data at falling edge, latch data at rising edge table 41. csi gated clock mode timing parameters id parameter symbol min. max. units p1 csi vsync to hsync time tv2h 67.5 ? ns p2 csi hsync setup time thsu 1 ? ns p3 csi data setup time tdsu 1 ? ns p4 csi data hold time tdh 1.2 ? ns p5 csi pixel clock high time tclkh 10 ? ns p6 csi pixel clock low time tclkl 10 ? ns p7 csi pixel clock frequency fclk ? 48 10% mhz table 42. csi ungated clock mode timing parameters id parameter symbol min. max. units p1 csi vsync to pixel clock time tvsync 67.5 ? ns p2 csi data setup time tdsu 1 ? ns p3 csi data hold time tdh 1.2 ? ns p4 csi pixel clock high time tclkh 10 ? ns p5 csi pixel clock low time tclkl 10 ? ns p6 csi pixel clock frequency fclk ? 48 10% mhz pixclk vsync data[15:0] p4 p1 p2 p3 p5 p6
i.mx25 applications processor for consumer and industrial products, rev. 9 54 freescale semiconductor 3.7.5 configurable serial peripheral interface (cspi) timing figure 23 and figure 24 provide cspi master and slave mode timing diagrams, respectively. table 43 describes the timing parameters (t1?t14) that are shown in the figures. the values shown in timing diagrams were tested using a worst-case core voltage of 1.1 v, slow pad voltage of 2.68 v, and fast pad voltage of 1.65 v. figure 23. cspi master mode timing diagram figure 24. cspi slave mode timing diagram t1 t10 t3 t2 ss n sclk mosi miso rdy (input) (output) t8 t6 t4 t4 t5 t7 t9 (output) t11 t12 t13 t1? t10 t3? t2? ss n sclk miso mosi (input) t4 t4 t5? t7? (input) t11 t12 t13 t6? t14 t14
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 55 3.7.6 external memory interface (emi) timing the emi module includes the enhanced sdram/lpddr memory controller (esdctl), nand flash controller (nfc), and wireless external interface module (weim). the following subsections give timing information for these submodules. table 43. cspi interface timing parameters id parameter description symbol minimum maximum units t1 cspi master sclk cycle time t clko 60.2 ? ns t2 cspi master sclk high time t clkoh 22.65 ? ns t3 cspi master sclk low time t clkol 22.47 ? ns t1? cspi slave sclk cycle time t clki 60.2 ? ns t2? cspi slave sclk high time t clkih 30.1 ? ns t3? cspi slave sclk low time t clkil 30.1 ? ns t4 cspi sclk transition time t pr 1 1 the output sclk transition time is tested with 25 pf drive. 2.6 8.5 ns t5 ss n output pulse width t wsso 2t sclk 2 +t wait 3 2 t sclk = cspi clock period 3 t wait = wait time, as specified in the sample period control register ?? t5? ss n input pulse width t wssi t per 4 4 t per = cspi reference baud rate clock period (perclk2) ?? t6 ss n output asserted to first sclk edge (ss output setup time) t ssso 3t sclk ?? t6? ss n input asserted to first sclk edge (ss input setup time) t sssi t per ?? t7 cspi master: last sclk edge to ss n negated (ss output hold time) t hsso 2t sclk ?? t7? cspi slave: last sclk edge to ss n negated (ss input hold time) t hssi 30 ? ns t8 cspi master: cspi1_rdy low to ss n asserted (cspi1_rdy setup time) t srdy 2t per 5t per ? t9 cspi master: ss n negated to cspi1_rdy low t hrdy 0?ns t10 output data setup time t sdatao (t clkol or t clkoh or t clkil or t clkih ) ? t ipg 5 5 t ipg = cspi main clock ipg_clock period ?? t11 output data hold time t hdatao t clkol or t clkoh or t clkil or t clkih ?? t12 input data setup time t sdatai t ipg + 0.5 ? ns t13 input data hold time t hdatai 0?ns t14 pause between data word t pause 0?ns
i.mx25 applications processor for consumer and industrial products, rev. 9 56 freescale semiconductor 3.7.6.1 esdctl electrical specifications 3.7.6.1.1 sdram memory controller the following diagrams and tables specify the timi ngs related to the sdramc module which interfaces sdram. figure 25. sdram read cycle timing diagram table 44. ddr/sdr sdram read cycle timing parameters id parameter symbol min. max. unit sd1 sdram clock high-level width 1 tch 3.4 4.1 ns sd2 sdram clock low-level width 1 tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sdclk we addr dq dqm col/ba data cs cas ras note: cke is high during the read/write cycle. sd4 sd1 sd3 sd2 sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd5 sd6 sd7 sd10 sd8 sd9 sdclk row/ba
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 57 figure 26. sdr sdram write cycle timing diagram sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd8 sdram access time tac ? 6.47 ns sd9 data out hold time 2 toh 1.2 ? ns sd10 active to read/write command period trc 10 ? clock 1 sd1 + sd2 does not exceed 7.5 ns for 133 mhz. 2 timing parameters are relevant only to sdr sdram. for the specific ddr sdram data related timing parameters, see ta b l e 4 8 and ta b l e 4 9 . table 44. ddr/sdr sdram read cycle timing parameters (continued) id parameter symbol min. max. unit cs cas we ras addr dq dqm ba row / ba col/ba data sd4 sd4 sd4 sd4 sd5 sd5 sd5 sd5 sd7 sd6 sd12 sd13 sd14 sd11 sdclk sd1 sd3 sd2 sdclk
i.mx25 applications processor for consumer and industrial products, rev. 9 58 freescale semiconductor figure 27. sdram refresh timing diagram table 45. sdr sdram write timing parameters id parameter symbol min. max. unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd4 cs, ras, cas, we, dqm, cke setup time tcms 2.0 ? ns sd5 cs, ras, cas, we, dqm, cke hold time tcmh 1.8 ? ns sd6 address setup time tas 2.0 ? ns sd7 address hold time tah 1.8 ? ns sd11 precharge cycle period 1 1 sd11 and sd12 are determined by sdram controller register settings. trp 1 4 clock sd12 active to read/write command delay 1 trcd 1 8 clock sd13 data setup time tds 2.0 ? ns sd14 data hold time tdh 1.3 ? ns cs cas we ras addr ba row/ba sd6 sd7 sd11 sd10 sd10 sdclk sd1 sd2 sdclk sd3
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 59 figure 28. sdram self-refresh cycle timing diagram note the clock continues to run unless cke is low. then the clock is stopped in low state. table 46. sdram refresh timing parameters id parameter symbol min. max. unit sd1 sdram clock high-level width tch 3.4 4.1 ns sd2 sdram clock low-level width tcl 3.4 4.1 ns sd3 sdram clock cycle time tck 7.5 ? ns sd6 address setup time tas 1.8 ? ns sd7 address hold time tah 1.8 ? ns sd10 precharge cycle period 1 1 sd10 and sd11 are determined by sdram controller register settings. trp 1 4 clock sd11 auto precharge command period 1 trc 2 20 clock sdclk cs cas ras addr ba we cke don?t care sd16 sd16
i.mx25 applications processor for consumer and industrial products, rev. 9 60 freescale semiconductor 3.7.6.1.2 mobile ddr sdram?specific parameters the following diagrams and tables specify the timi ngs related to the sdramc module which interfaces with the mobile ddr sdram. figure 29. mobile ddr sdram write cycle timing diagram table 47. sdram self-refresh cycle timing parameters id parameter symbol min. max. unit sd16 cke output delay time tcks 1.8 ? ns table 48. mobile ddr sdram write cycle timing parameters 1 1 test condition: measured using delay line 5 programmed as follows: esdcdly5[15:0] = 0x0703. id parameter symbol min. max. unit sd17 dq and dqm setup time to dqs tds 0.95 ? ns sd18 dq and dqm hold time to dqs tdh 0.95 ? ns sd19 write cycle dqs falling edge to sdclk output delay time tdss 1.8 ? ns sd20 write cycle dqs falling edge to sdclk output hold time tdsh 1.8 ? ns sdclk sdclk dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm sd17 sd17 sd17 sd17 sd18 sd18 sd18 sd18 sd19 sd20
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 61 figure 30. mobile ddr sdram dq versus dqs and sdclk read cycle timing diagram table 49. mobile ddr sdram read cycle timing parameters id parameter symbol min. max. unit sd21 dqs ? dq skew (defines the data valid window in read cycles related to dqs) tdqsq ? 0.85 ns sd22 dqs dq hold time from dqs tqh 2.3 ? ns sd23 dqs output access time from sdclk posedge tdqsck ? 6.7 ns sdclk sdclk dqs (input) dq (input) data data data data data data data data sd23 sd21 sd22
i.mx25 applications processor for consumer and industrial products, rev. 9 62 freescale semiconductor 3.7.6.1.3 ddr2 sdram?specific parameters the following diagrams and tables specify timing related to the sdramc module, which interfaces with ddr2 sdram. figure 31. ddr2 sdram basic timing parameters table 50 provides values for a command/address slew rate of 1 v/ns and an sdclk, sdclk_b differential slew rate of 2 v/ns. for additional values, use table 51 , ?tls, tlh derating values for ddr2-400, ddr2-533.? table 50. ddr2 sdram timing parameter table id parameter symbol ddr2-400 unit min. max. ddr1 sdram clock high-level width t ch 0.45 0.55 t ck ddr2 sdram clock low-level width t cl 0.45 0.55 t ck ddr3 sdram clock cycle time t ck 7.5 8 ns sdclk we addr row/ba col/ba cs cas ras ddr1 ddr3 ddr2 ddr4 ddr4 ddr4 ddr5 ddr5 ddr5 ddr5 ddr6 ddr7 sdclk cke ddr4 ddr4
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 63 table 50 shows values for a command/address slew rate of 1 v/ns and an sdclk, sdclk_b differential slew rate of 2 v/ns. table 51 shows additional values for ddr2-400 and ddr2-533. ddr4 cs, ras, cas, cke, we setup time t is 0.35 ? ns ddr5 cs, ras, cas, cke, we hold time t ih 0.475 ? ns ddr6 address output setup time t is 0.35 ? ns ddr7 address output hold time t ih 0.475 ? ns table 51. tls, tlh derating values for ddr2-400, ddr2-533 command/ address slew rate (v/ns) ck, ck differential slew rate units 2.0 v/ns 1.5 v/ns 1.0 v/ns tls tlh tls tlh tls tlh 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 ?11 ?14 +19 +16 +49 +46 ps 0.8 ?25 ?31 +5 ?1 +35 +29 ps 0.7 ?43 ?54 ?13 ?24 +17 +6 ps 0.6 ?67 ?83 ?37 ?53 ?7 ?23 ps 0.5 ?110 ?125 ?80 ?95 ?50 ?65 ps 0.4 ?175 ?188 ?145 ?158 ?115 ?128 ps 0.3 ?285 ?292 ?255 ?262 ?225 ?232 ps 0.25 ?350 ?375 ?320 ?345 ?290 ?315 ps 0.2 ?525 ?500 ?495 ?470 ?465 ?440 ps 0.15 ?800 ?708 ?770 ?678 ?740 ?648 ps 0.1 ?1450 ?1125 ?1420 ?1095 ?1390 ?1065 ps table 50. ddr2 sdram timing parameter table (continued) id parameter symbol ddr2-400 unit min. max.
i.mx25 applications processor for consumer and industrial products, rev. 9 64 freescale semiconductor figure 32. ddr2 sdram write cycle timing diagram table 52. ddr2 sdram write cycle parameter table id parameter symbol ddr2-400 unit min. max. ddr17 dq & dqm setup time to dqs (single-ended strobe) 1 1 these values are for a dq/dm slew rate of 1 v/ns and a dqs slew rate of 1 v/ns. for additional values use ta ble 5 3 , ?dtds1, dtdh1 derating values for ddr2-400, ddr2-533.? t ds1(base) 0.025 ? ns ddr18 dq & dqm hold time to dqs (single-ended strobe) 1 t dh1(base) 0.025 ? ns ddr19 write cycle dqs falling edge to sdclk output setup time t dss 0.2 ? tck ddr20 write cycle dqs falling edge to sdclk output hold time t dsh 0.2 ? tck ddr21 dqs latching rising transitions to associated clock edges t dqss -0.25 0.25 tck ddr22 dqs high-level width t dqsh 0.35 ? tck ddr23 dqs low-level width t dqsl 0.35 ? tck table 53. tds1, tdh1 derating values for ddr2-400, ddr2-533 1,2,3 dqs single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 vns 0.4 v/ns td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 td s1 td h1 sdclk sdclk_b dqs (output) dq (output) dqm (output) data data data data data data data data dm dm dm dm dm dm dm dm ddr17 ddr17 ddr17 ddr17 ddr18 ddr18 ddr18 ddr18 ddr19 ddr20 ddr21 ddr23 ddr22
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 65 figure 33. ddr2 sdram dq vs. dqs and sdclk read cycle timing diagram dq slew rate v/ns 2.018818816714612563???? ???????? 1.514616712512583428143?????????? 1.06312542830 0?21?7?13???????? 0.9??3169?11?14?13?13?18?27?29?45?????? 0.8?????25?31?27?30?32?44?43?62?60?86 ???? 0.7???????45?53?50?67?61?85?78?109?108?152?? 0.6?????????74?96?85?114?102?138?132?181?183?246 0.5???????????128?156?145?180?175?223?226?288 0.4?????????????210?243?240?286?291?351 1 all units in ?ps?. 2 test conditions are at capacitance=15pf for ddr pads. recommended drive strengths are medium for sdclk and high for address and controls. 3 sdram clk and dqs related parameters are measured from the 50% point. that is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock). table 54. ddr2 sdram read cycle parameter table 1,2 1 test conditions are at capacitance=15 pf for ddr pads. recommended drive strengths are medium for sdclk and high for address and controls. id parameter symbol ddr2-400 unit min. max. ddr24 dqs - dq skew (defines the data valid window in read cycles related to dqs) t dqsq ?0.35ns ddr25 dqs dq in hold time from dqs 3 t qh 2.925 ? ns ddr26 dqs output access time from sdclk posedge t dqsck ?0.5 0.5 ns table 53. tds1, tdh1 derating values for ddr2-400, ddr2-533 1,2,3 (continued) dqs single-ended slew rate sdclk sdclk_b dqs (input) dq (input) data data data data data data data data ddr26 ddr24 ddr25
i.mx25 applications processor for consumer and industrial products, rev. 9 66 freescale semiconductor 3.7.6.2 nand flash controller (nfc) timing the i.mx25 nfc supports normal timing mode, using two flash clock cycles for one access of re and we . ac timings are provided as multiplications of the clock cycle and fixed delay. figure 34 through figure 37 depicts the relative timing betw een nfc signals at the module level for different operations under normal mode. table 55 describes the timing parameters (nf1?nf17) that are shown in the figures. figure 34. command latch cycle timing diagram figure 35. address latch cycle timing diagram 2 sdram clk and dqs-related parameters are measured from the 50% point. that is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. ddr sdram clk parameters are measured at the crossing point of sdclk and sdclk (inverted clock). 3 the value was calculated for an sdclk frequency of 133 mhz, by the formula tqh = thp ? tqhs = min. (tcl,tch) ? tqhs = 0.45*tck ? tqhs = 0.45 * 7.5 ? 0.45 = 2.925 ns nfcle nfce nfwe nfale nfio[7:0] command nf9 nf8 nf1 nf2 nf5 nf3 nf4 nf6 nf7 nfcle nfce nfwe nfale nfio[7:0] address nf9 nf8 nf1 nf5 nf3 nf4 nf6 nf11 nf10 nf7
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 67 figure 36. write data latch cycle timing diagram figure 37. read data latch cycle timing diagram table 55. nfc timing parameters 1 id parameter symbol timing t = nfc clock cycle example timing for nfc clock 33 mhz t = 30 ns unit min. max. min. max. nf1 nfcle setup time tcls t?1.0 ns ? 29 ? ns nf2 nfcle hold time tclh t?2.0 ns ? 28 ? ns nf3 nfce setup time tcs 2t?5.0 ns ? 55 ? ns nf4 nfce hold time tch 7t?5.0 ns ? 205 ? ns nfcle nfce nfwe nfale nfio[15:0] data to nf nf9 nf8 nf1 nf5 nf3 nf6 nf11 nf10 nf7 nfcle nfce nfre nfrb nfio[15:0] data from nf nf13 nf15 nf14 nf17 nf12 nf16
i.mx25 applications processor for consumer and industrial products, rev. 9 68 freescale semiconductor note for timing purposes, transition to signal high is defined as 80% of signal value; while signal low is defined as 20% of signal value. timing for hclk is 133 mhz. the internal nfc clock (flash clock) is approximately 33 mhz (30 ns). all timings are listed according to this nfc clock frequency (multiples of nfc clock phases), except nf16 and nf17, which are not related to the nfc clock. 3.7.6.3 wireless external interface module (weim) timing figure 38 depicts the timing of the weim module, and table 56 describes the timing parameters (we1?we27) shown in the figure. all weim output control signals may be asserted and negated by internal cloc k relative to bclk rising edge or falling edge according to corresponding asser tion/negation control fields. address always begins relative to bclk falling edge, but may be ended on rising or falling edge in muxed mode according to the control register configuration. output data begins relative to bclk rising edge except in muxed mode, where rising or falling edge may be used according to the control register configuration. input data, ecb and dtack are all captured relative to bclk rising edge. nf5 nf_wp pulse width twp t?1.5 ns 28.5 ns nf6 nfale setup time tals t ? 30 ? ns nf7 nfale hold time talh t?3.0 ns ? 27 ? ns nf8 data setup time tds 2t ns ? 60 ? ns nf9 data hold time tdh t?5.0 ns ? 25 ? ns nf10 write cycle time twc 2t 60 ns nf11 nfwe hold time twh t?2.5 ns 27.5 ns nf12 ready to nfre low trr 21t?10 ns ? 620 ? ns nf13 nfre pulse width trp 1.5t ? 45 ? ns nf14 read cycle time trc 2t ? 60 ? ns nf15 nfre high hold time treh 0.5t?2.5 ns 12.5 ? ns nf16 data setup on read tdsr n/a 10 ? ns nf17 data hold on read tdhr n/a 0 ? ns 1 the flash clock maximum frequency is 50 mhz. table 55. nfc timing parameters 1 (continued) id parameter symbol timing t = nfc clock cycle example timing for nfc clock 33 mhz t = 30 ns unit min. max. min. max.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 69 figure 38. weim bus timing diagram table 56. weim bus timing parameters 1 id parameter min. max. unit we1 bclk cycle time 2 14.5 ? ns we2 bclk low-level width 2 7?ns we3 bclk high-level width 2 7?ns we4 clock fall to address valid 15 21 ns we5 clock rise/fall to address invalid 22 25 ns we6 clock rise/fall to cs [x] valid 15 19 ns we7 clock rise/fall to cs [x] invalid 3.3 5 ns weim output timing weim input timing we4 address cs [x] rw oe bclk eb [y] lba output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data ecb dtack bclk we20, we21 we18, we19 we24, we25 we22, we23 we27 we26
i.mx25 applications processor for consumer and industrial products, rev. 9 70 freescale semiconductor note the test condition load capacitance was 25 pf. recommended drive strength for all controls, address, and bclk is maximum drive. recommended drive strength for all controls, address and bclk is maximum drive. we8 clock rise/fall to rw valid 8 12 ns we9 clock rise/fall to rw invalid 3 8 ns we10 clock rise/fall to oe valid 7 12 ns we11 clock rise/fall to oe invalid 3.6 5.5 ns we12 clock rise/fall to eb [y] valid 6 11.5 ns we13 clock rise/fall to eb [y] invalid 6 10 ns we14 clock rise/fall to lba valid 17.5 20 ns we15 clock rise/fall to lba invalid 0 1 ns we16 clock rise/fall to output data valid 5 10 ns we17 clock rise to output data invalid 0 2.5 ns we18 input data valid to clock rise, fce=1 1 ? ns we19 input data valid to clock rise, fce=0 (in the case there is ecb asserted during access) 1/2 bclk +2.63 ?ns input data valid to clock rise, fce=0 (in the case there is no ecb asserted during access) 6.9 ? ns we20 clock rise to input data invalid, fce=1 1 ? ns we21 clock rise to input data invalid, fce=0 2.4 ? ns we22 ecb setup time, fce=1 5 ? ns we23 ecb setup time, fce=0 7.2 ? ns we24 ecb hold time, fce=1 5 ? ns we25 ecb hold time, fce=0 0 ? ns we26 dtack setup time 5.4 ? ns we27 dtack hold time ?3.2 ? ns 1 high is defined as 80% of signal value; low is defined as 20% of signal value. 2 bclk parameters are being measured from the 50% point. for example, high is defined as 50% of signal value and low is defined as 50% as signal value. table 56. weim bus timing parameters 1 (continued) id parameter min. max. unit
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 71 figure 39 through figure 44 give examples of basic weim accesses to external memory devices with the timing parameters described in table 56 for specific control parameter settings. figure 39. synchronous memory timing diagram for read access?wsc=1 figure 40. synchronous memory timing diagram for write access? wsc=1, ebwa=1, ebwn=1, lbn=1 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we19 we21 last valid address v1 v1 bclk addr data rw lba oe eb [y] cs [x] next address we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17
i.mx25 applications processor for consumer and industrial products, rev. 9 72 freescale semiconductor figure 41. synchronous memory timing diagram for two non-sequential read accesses? wsc=2, sync=1, dol=0 last valid addr address v1 address v2 v1 v1+2 v2 v2+2 bclk addr ecb data halfword halfword cs [x] rw lba oe eb [y] halfword halfword we4 we5 we7 we10 we11 we12 we13 we14 we15 we18 we18 we19 we19 we22 we22 we24 we24 we6
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 73 figure 42. synchronous memory timing diagram for burst write access? bcs=1, wsc=4, sync=1, dol=0, psr=1 figure 43. muxed a/d mode timing diagram for synchronous write access? wsc=7, lba=1, lbn=1, lah=1 last valid addr bclk addr data cs [x] rw lba oe eb [y] ecb address v1 v1 v1+4 v1+12 v1+8 we12 we4 we5 we6 we7 we8 we9 we13 we14 we16 we16 we17 we17 we22 we24 we15 write bclk addr/ rw lba oe eb [y] cs [x] address v1 write data last valid addr m_data we4 we5 we6 we7 we9 we8 we12 we13 we14 we15 we16 we17
i.mx25 applications processor for consumer and industrial products, rev. 9 74 freescale semiconductor figure 44. muxed a/d mode timing diagram for synchronous read access? wsc=7, lba=1, lbn=1, lah=1, oea=7 figure 45 through figure 49 , and ta ble 57 help to determine timing parameters relative to chip select (cs) state for asynchronous and dtack weim accesses with corresponding weim bit fields and the timing parameters mentioned above. figure 45. asynchronous memory read access bclk addr/ rw lba oe eb [y] cs [x] address v1 read data last valid addr m_data we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we20 we4 last valid address address v1 v1 addr data rw lba oe eb [y ] cs [x] next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 75 figure 46. asynchronous a/d muxed read access (rwsc = 5) figure 47. asynchronous memory write access addr. v1 d(v1) addr/ we lba oe eb [y] cs [x] we39 we35a we37 we36 we38 we40 we31 we44 maxdi maxco we32a m_data last valid address address v1 d(v1) addr data r w lba oe eb [y] cs [x] next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41
i.mx25 applications processor for consumer and industrial products, rev. 9 76 freescale semiconductor figure 48. asynchronous a/d mux write access figure 49. dtack read access table 57. weim asynchronous timing parameters relative to chip select table ref no. parameter determination by synchronous measured parameters 1 min max (if 133 mhz is supported by soc) unit we31 cs [x] valid to address valid we4 ? we6 ? csa 2 ? 3 ? csa ns we32 address invalid to cs [x] invalid we7 ? we5 ? csn 3 ?3 ? csnns r w oe eb [y] cs [x] we33 we45 we34 we46 we42 addr. v1 d(v1) addr/ we31 we42 we41 we32a m_data lba we39 we40a last valid address address v1 v1 addr data rw lba oe eb [y ] cs [x] next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 data we47 we48
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 77 we32a( muxed a/d cs [x] valid to address invalid we4 ? we7 + (lbn + lba + 1 ? csa 2 ) ?3 + (lbn + lba + 1 ? csa) ?ns we33 cs [x] valid to rw valid we8 ? we6 + (rwa ? csa) ? 3 + (rwa ? csa) ns we34 rw invalid to cs [x] invalid we7 ? we9 + (rwn ? csn) ? 3 ? (rwn_csn) ns we35 cs [x] valid to oe valid we10 ? we6 + (oea ? csa) ? 3 + (oea ? csa) ns we35a (muxed a/d) cs [x] valid to oe valid we10 ? we6 + (oea + lbn + lba + lah + 1 ? csa) ?3 + (oea + lbn + lba + lah + 1 ? csa) 3 + (oea + lbn + lba + lah + 1 ? csa) ns we36 oe invalid to cs [x] invalid we7 ? we11 + (oen ? csn) ? 3 ? (oen ? csn) ns we37 cs [x] valid to eb [y] valid (read access) we12 ? we6 + (ebra ? csa) ? 3 + (ebra 4 ? csa) ns we38 eb [y] invalid to cs [x] invalid (read access) we7 ? we13 + (ebrn ? csn) ? 3 ? (ebrn 5 ? csn) ns we39 cs [x] valid to lba valid we14 ? we6 + (lba ? csa) ? 3 + (lba ? csa) ns we40 lba invalid to cs [x] invalid we7 ? we15 ? csn ? 3 ? csn ns we40a (muxed a/d) cs [x] valid to lba invalid we14 ? we6 + (lbn + lba + 1 ? csa) ?3 + (lbn + lba + 1 ? csa) 3 + (lbn + lba + 1 ? csa) ns we41 cs [x] valid to output data valid we16 ? we6 ? csa ? 3 ? csa ns we41a (muxed a/d) cs [x] valid to output data valid we16 ? we6 + (lbn + lba + lah + 1 ? csa) ? 3 + (lbn + lba + lah + 1 ? csa) ns we42 output data invalid to cs [x] invalid we17 ? we7 ? csn ? 3 ? csn ns we43 input data valid to cs [x] invalid maxco ? maxcso + maxdi maxco 6 ? maxcso 7 + maxdi 8 ?ns we44 cs [x] invalid to input data invalid 00?ns we45 cs [x] valid to eb [y] valid (write access) we12 ? we6 + (ebwa ? csa) ? 3 + (ebwa ? csa) ns we46 eb [y] invalid to cs [x] invalid (write access) we7 ? we13 + (ebwn ? csn) ? ?3 + (ebwn ? csn) ns we47 dtack valid to cs [x] invalid maxco ? maxcso + maxdti maxco 6 ? maxcso 7 + maxdti 9 ?ns we48 cs [x] invalid to dtack invalid 0 0 ? ns table 57. weim asynchronous timing parameters relative to chip select table (continued) ref no. parameter determination by synchronous measured parameters 1 min max (if 133 mhz is supported by soc) unit
i.mx25 applications processor for consumer and industrial products, rev. 9 78 freescale semiconductor note all configuration parameters (csa, csn, ebwa, ebwn, lba, lbn, lah, oen, oea, ebra, and ebrn) are in cycle units. 1 for the value of parameters we4?we21, see column bcd = 0 in ta b l e 5 6 . 2 cs assertion. this bit field determines when the cs signal is asserted during read/write cycles. 3 cs negation. this bit field determines when the cs signal is negated during read/write cycles. 4 be assertion. this bit field determines when the be signal is asserted during read cycles. 5 be negation. this bit field determines when the be signal is negated during read cycles. 6 output maximum delay from internal driving addr/control ffs to chip outputs. 7 output maximum delay from cs [x] internal driving ffs to cs [x] out. 8 data maximum delay from chip input data to its internal ff. 9 dtack maximum delay from chip dtack input to its internal ff.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 79 3.7.7 enhanced serial audio interface (esai) timing this section describes general timi ng requirements for esai, as well as the esai transmit and receive timing. figure 50 shows the esai transmit timing diagram. figure 50. esai transmit timing see note sckt (input/output) fst (bit) out fst (word) out data out transmitter #0 drive enable (internal signal) fst (bit) in fst (word) in flags out note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. 62 64 78 79 82 83 87 86 86 84 93 88 85 91 89 92 90 91 94 63 last bit first bit
i.mx25 applications processor for consumer and industrial products, rev. 9 80 freescale semiconductor figure 51 shows the esai receive timing diagram. figure 51. esai receive timing diagram figure 52 shows the esai hckt timing diagram. figure 52. esai hckt timing sckr (input/output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in 62 64 65 69 70 72 71 75 73 74 75 77 76 63 66 first bit last bit hckt sckt (output) 96 95
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 81 figure 53 shows the esai hckr timing diagram. figure 53. esai hckr timing table 60 describes the general timing requirements for the esai module. table 58 and table 59 describe respectively the conditions and signals cited in table 60 . table 58. esai timing conditions symbol significance comments i ck internal clock in the i.mx25, the internal clock frequency is equal to the ip bus frequency (133 mhz) x ck external clock the external clock may be derived from the crm module or other external clock sources i ck a internal clock, asynchronous mode in asynchronous mode, sckt and sckr are different clocks i ck s internal clock, synchronous mode in synchronous mode, sckt and sckr are the same clock table 59. esai signals signal name significance sckt transmit clock sckr receive clock fst transmit frame sync hckt transmit high-frequency clock hckr receive high-frequency clock table 60. esai general timing requirements no. characteristics 1 2 symbol expression 3 min. max. condition unit 62 clock cycle 4 t ssicc 4 t c 4 t c 30.0 30.0 ? ? i ck i ck ns 63 clock high period for internal clock ? ? ? 2 t c ? 9.0 ? 6 ? ? ?ns for external clock ? 2 t c 15 ? ? 64 clock low period for internal clock ?2 t c ? 9.0 6 ? ?ns for external clock ? 2 t c 15 ? ? hckr sckr (output) 97 95
i.mx25 applications processor for consumer and industrial products, rev. 9 82 freescale semiconductor 65 sckr rising edge to fsr out (bl) high ? ? ? ? 17.0 7.0 x ck i ck a ns 66 sckr rising edge to fsr out (bl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 67 sckr rising edge to fsr out (wr) high 5 ??? ? 19.0 9.0 x ck i ck a ns 68 sckr rising edge to fsr out (wr) low 5 ??? ? 19.0 9.0 x ck i ck a ns 69 sckr rising edge to fsr out (wl) high ? ? ? ? 16.0 6.0 x ck i ck a ns 70 sckr rising edge to fsr out (wl) low ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time before sckr (sck in synchronous mode) falling edge ??12.0 19.0 ? ? x ck i ck ns 72 data in hold time after sckr falling edge ? ? 3.5 9.0 ? ? x ck i ck ns 73 fsr input (bl, wr) high before sckr falling edge 5 ??2.0 12.0 ? ? x ck i ck a ns 74 fsr input (wl) high before sckr fa lling edge ? ? 2.0 12.0 ? ? x ck i ck a ns 75 fsr input hold time after sckr falling edge ? ? 2.5 8.5 ? ? x ck i ck a ns 76 flags input setup before sckr falling edge ? ? 0.0 19.0 ? ? x ck i ck s ns 77 flags input hold time after sckr falling edge ? ? 6.0 0.0 ? ? x ck i ck s ns 78 sckt rising edge to fst out (bl) high ? ? ? ? 18.0 8.0 x ck i ck ns 79 sckt rising edge to fst out (bl) low ? ? ? ? 20.0 10.0 x ck i ck ns 80 sckt rising edge to fst out (wr) high 5 ??? ? 20.0 10.0 x ck i ck ns 81 sckt rising edge to fst out (wr) low 5 ??? ? 22.0 12.0 x ck i ck ns 82 sckt rising edge to fst out (wl) high ? ? ? ? 19.0 9.0 x ck i ck ns 83 sckt rising edge to fst out (wl) low ? ? ? ? 20.0 10.0 x ck i ck ns 84 sckt rising edge to data out enable from high impedance ??? ? 22.0 17.0 x ck i ck ns 85 sckt rising edge to transmitter #0 drive enable assertion ??? ? 17.0 11.0 x ck i ck ns table 60. esai general timing requirements (continued) no. characteristics 1 2 symbol expression 3 min. max. condition unit
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 83 3.7.8 enhanced secured digital host controller (esdhcv2) timing figure 54 shows esdhcv2 timing, and table 61 describes the timing parameters (sd1?sd8) used in the figure. the following definitions apply to values and signals described in table 61 : ? ls: low-speed mode. low-speed card can tolerate clocks up to 400 khz ? fs: full-speed mode. full-speed mmc card?s clock can reach 20 mhz; full speed sd/sdio card clock can reach 25 mhz ? hs: high-speed mode. high-speed mmc card?s clock can reach 52 mhz; sd/sdio card clock can reach 50 mhz 86 sckt rising edge to data out valid ? ? ? ? 18.0 13.0 x ck i ck ns 87 sckt rising edge to data out high impedance 6 ??? ? 21.0 16.0 x ck i ck ns 88 sckt rising edge to transmitter #0 drive enable negation 6 ??? ? 14.0 9.0 x ck i ck ns 89 fst input (bl, wr) setup time before sckt falling edge 5 ??2.0 18.0 ? ? x ck i ck ns 90 fst input (wl) setup time before sckt falling edge ??2.0 18.0 ? ? x ck i ck ns 91 fst input hold time after sckt falling edge ? ? 4.0 5.0 ? ? x ck i ck ns 92 fst input (wl) to data out enable from high impedance ? ? ? 21.0 ? ns 93 fst input (wl) to transmitter #0 drive enable assertion ? ? ? 14.0 ? ns 94 flag output valid after sckt rising edge ? ? ? ? 14.0 9.0 x ck i ck ns 95 hckr/hckt clock cycle ? 2 x t c 15 ? ? ns 96 hckt input rising edge to sckt output ? ? ? 18.0 ? ns 97 hckr input rising edge to sckr output ? ? ? 18.0 ? ns 1 v core_vdd = 1.00 0.10 v; t j = ?40 c to 125 c, c l = 50 pf 2 in the ?characteristics? column, bl = bit length, wl = word length, wr = word length relative 3 in the ?expression? column, t c = 7.5 ns. 4 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 5 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signa l), until the second-to-last bit-clock of the first word in the frame. 6 periodically sampled and not 100% tested. table 60. esai general timing requirements (continued) no. characteristics 1 2 symbol expression 3 min. max. condition unit
i.mx25 applications processor for consumer and industrial products, rev. 9 84 freescale semiconductor figure 54. esdhcv2 timing table 61. esdhcv2 interface timing specification id parameter symbols min. max. unit card input clock sd1 clock frequency (low speed) f pp 1 1 in low-speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 0400khz clock frequency (sd/sdio full speed/high speed) f pp 2 2 in normal-speed mode for sd/sdio card, clock frequency can be any value between 0 ~ 25 mhz. in high speed mode, clock frequency can be any value between 0 ~ 50 mhz. 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 3 in normal-speed mode for mmc card, clock frequency can be any value between 0 ~ 20 mhz. in high speed mode, clock frequency can be any value between 0 ~ 52 mhz. 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 6.5 ? ns sd3 clock high time t wh 6.5 ? ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns esdhc output / card inputs cmd, dat (reference to clk) sd6 esdhc output delay t od ?33ns esdhc input / card outputs cmd, dat (reference to clk) sd7 esdhc input setup time t isu 2.5 ? ns sd8 esdhc input hold time t ih 4 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 2.5 ? ns sd1 sd3 sd5 sd4 sd7 cmd output from esdhcv2 to card dat1 ...... dat7 dat0 cmd input from card to esdhcv2 dat1 ...... dat3 dat0 clk sd2 sd8 sd6
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 85 3.7.9 fast ethernet controller (fec) timing the fec is designed to support both 10- and 100-mbps ethernet networks compliant with the ieee 802.3 standard. an external transceiver interface and transceiver function are required to complete the interface to the media. the fec supports 10/100 mbps mii (18 pins altogether), 10/100 mbps rmii (ten pins, including serial management interface) and the 10-mbps-only 7-wire interface (which uses seven of the mii pins), for connection to an external ethernet transceiver. all signals are compatible with transceivers operating at a voltage of 3.3 v. the following subsections describe the timing for mii and rmii modes. 3.7.9.1 fec mii mode timing the following subsections describe mii receive, tr ansmit, asynchronous inputs, and serial management signal timings. 3.7.9.1.4 mii receive signal timing (fec_rxd[3:0], fec_rx_dv, fec_rx_er, and fec_rx_clk) the receiver functions correctly up to an fec_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the pr ocessor clock frequency must exceed twice the fec_rx_clk frequency. figure 55 shows mii receive signal timings. table 62 describes the timing parameters (m1?m4) shown in the figure. figure 55. mii receive signal timing diagram 1 fec_rx_dv, fec_rx_clk, and fec_rxd0 have the same timing in 10 mbps 7-wire interface mode. table 62. mii receive signal timing id characteristic 1 min. max. unit m1 fec_rxd[3:0], fec_rx_dv, fec_rx_er to fec_rx_clk setup 5 ? ns m2 fec_rx_clk to fec_rxd[3:0], fec_rx_dv, fec_rx_er hold 5 ? ns m3 fec_rx_clk pulse width high 35% 65% fec_rx_clk period m4 fec_rx_clk pulse width low 35% 65% fec_rx_clk period fec_rx_clk (input) fec_rxd[3:0] (inputs) fec_rx_dv fec_rx_er m3 m4 m1 m2
i.mx25 applications processor for consumer and industrial products, rev. 9 86 freescale semiconductor 3.7.9.1.5 mii transmit signal timing (fec_txd[3:0], fec_tx_en, fec_tx_er, and fec_tx_clk) the transmitter functions correctly up to an fec_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the processor clock frequency must exceed twice the fec_tx_clk frequency. figure 56 shows mii transmit signal timings. table 63 describes the timing parameters (m5?m8) shown in the figure. figure 56. mii transmit signal timing diagram 1 fec_tx_en, fec_tx_clk, and fec_txd0 have the same timing in 10-mbps 7-wire interface mode. 3.7.9.1.6 mii asynchronous inputs signal timing (fec_crs and fec_col) figure 57 shows mii asynchronous input timings. table 64 describes the timing parameter (m9) shown in the figure. figure 57. mii async inputs timing diagram table 63. mii transmit signal timing id characteristic 1 min. max. unit m5 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er invalid 5 ? ns m6 fec_tx_clk to fec_txd[3:0], fec_tx_en, fec_tx_er valid ? 20 ns m7 fec_tx_clk pulse width high 35% 65% fec_tx_clk period m8 fec_tx_clk pulse width low 35% 65% fec_tx_clk period fec_tx_clk (input) fec_txd[3:0] (outputs) fec_tx_en fec_tx_er m7 m8 m5 m6 fec_crs, fec_col m9
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 87 1 fec_col has the same timing in 10-mbit 7-wire interface mode. 3.7.9.2 mii serial management channel timing (fec_mdio and fec_mdc) the mdc frequency is designed to be equal to or less than 2.5 mhz to comply with the ieee 802.3 standard mii specification. however the fec can function correctly with a maximum mdc frequency of 15 mhz. figure 58 shows mii asynchronous input timings. table 65 describes the timing parameters (m10?m15) shown in the figure. figure 58. mii serial management channel timing diagram table 64. mii asynchronous inputs signal timing id characteristic min. max. unit m9 1 fec_crs to fec_col minimum pulse width 1.5 ? fec_tx_clk period table 65. mii serial management channel timing id characteristic min. max. unit m10 fec_mdc falling edge to fec_mdio output invalid (min. propagation delay) 0? ns m11 fec_mdc falling edge to fec_mdio output valid (max. propagation delay) ?5 ns m12 fec_mdio (input) to fec_mdc rising edge setup 18 ? ns m13 fec_mdio (input) to fec_mdc rising edge hold 0 ? ns m14 fec_mdc pulse width high 40% 60% fec_mdc period m15 fec_mdc pulse width low 40% 60% fec_mdc period fec_mdc (output) fec_mdio (output) m14 m15 m10 m11 m12 m13 fec_mdio (input)
i.mx25 applications processor for consumer and industrial products, rev. 9 88 freescale semiconductor 3.7.9.3 rmii mode timing in rmii mode, fec_tx_clk is used as the ref_clk, which is a 50 mhz 50 ppm continuous reference clock. fec_rx_dv is used as the crs_ dv in rmii. other signals under rmii mode include fec_tx_en, fec_txd[1:0], fec_rxd[1:0] and fec_rx_er. figure 59 shows rmii mode timings. table 66 describes the timing parameters (m16?m21) shown in the figure. figure 59. rmii mode signal timing diagram table 66. rmii signal timing id characteristic min. max. unit m16 ref_clk(fec_tx_clk) pulse width high 35% 65% ref_clk period m17 ref_clk(fec_tx_clk) pulse width low 35% 65% ref_clk period m18 ref_clk to fec_txd[1:0], fec_tx_en invalid 3 ? ns m19 ref_clk to fec_txd[1:0], fec_tx_en valid ? 12 ns m20 fec_rxd[1:0], crs_dv(fec_rx_dv), fec_rx_er to ref_clk setup 2 ? ns m21 ref_clk to fec_rxd[1:0], fec_rx_dv, fec_rx_er hold 2 ? ns ref_clk (input) fec_tx_en m16 m17 m18 m19 m20 m21 fec_rxd[1:0] fec_txd[1:0] (output) fec_rx_er crs_dv (input)
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 89 3.7.10 controller area network (flexcan) transceiver parameters and timing table 67 and table 68 show voltage requirements for the flexcan transceiver tx and rx pins. figure 60 through figure 63 show the flexcan timing, including timing of the standby and shutdown signals. figure 60. flexcan timing diagram table 67. tx pin characteristics parameter symbol min. typ. max. units high-level output voltage v oh 2? vcc 1 + 0.3 1 vcc = +3.3 v 5% v low-level output voltage v ol ?0.8 ? v table 68. rx pin characteristics parameter symbol min. typ. max. units high-level input voltage v ih 0.8 vcc 1 1 vcc = +3.3 v 5% ? vcc 1 v low-level input voltage v il ?0.4 ? v txd v diff rxd v cc /2 t ontxd t offtxd t onrxd t offrxd v cc /2 v cc /2 0.5v 0.9v v cc /2
i.mx25 applications processor for consumer and industrial products, rev. 9 90 freescale semiconductor figure 61. timing diagram for flexcan standby signal figure 62. timing diagram for flexcan shutdown signal figure 63. timing diagram for flexcan shutdown-to-standby signal because integer multiples are not possible, taking into account the range of frequencies at which the soc has to operate, dplls work in fol mode only. rs v diff rxd v cc /2 v cc /2 t sbrxdl t drxdl 1.1v v cc x 0.75 bus externally driven shdn v diff rxd v cc /2 v cc /2 bus externally driven t offshdn t onshdn v cc /2 0.5v shdn rs v cc /2 0.75 x v cc t shdnsb
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 91 3.7.11 inter ic communication (i 2 c) timing the i 2 c communication protocol consists of the following seven elements: ?start ? data source/recipient ? data direction ? slave acknowledge ?data ? data acknowledge ? stop figure 64 shows the timing of the i 2 c module. table 69 and table 70 describe the i 2 c module timing parameters (ic1?ic6) shown in the figure. figure 64. i 2 c module timing diagram table 69. i2c module timing parameters: 3.0 v +/?0.30 v id parameter standard mode fast mode unit min. max. min. max. ic1 i2clk cycle time 10 - 2.5 s ic2 hold time (repeated) start condition 4.0 - 0.6 - s ic3 set-up time for stop condition 4.0 - 0.6 - s ic4 data hold time 0 1 3.45 2 0 1 0.9 2 s ic5 high period of i2clk clock 4.0 - 0.6 - s ic6 low period of the i2clk clock 4.7 - 1.3 - s ic7 set-up time for a repeated start condition 4.7 - 0.6 - s ic8 data set-up time 250 - 100 3 -ns ic9 bus free time between a stop and start condition 4.7 - 1.3 - s ic10 rise time of both i2dat and i2clk signals - 1000 20+0.1c b 4 300 ns ic11 fall time of both i2dat and i2clk signals - 300 20+0.1c b 4 300 ns ic12 capacitive load for each bus line (c b ) - 400 - 400 pf ic10 ic11 ic9 ic2 ic8 ic4 ic7 ic3 ic6 ic10 ic5 ic11 start stop start start i2dat i2clk ic1
i.mx25 applications processor for consumer and industrial products, rev. 9 92 freescale semiconductor 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2clk signal 3 a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement of set-up time (id no ic7) of 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the i2clk signal. if such a device does stretch the low period of the i2clk signal, it must output the next data bit to the i2dat line max_rise_time(id no ic9) + data_setup_time(id no ic7) = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the i2clk line is released. 4 c b = total capacitance of one bus line in pf. table 70. i2c module timing parameters: 1.8 v +/? 0.10 v id parameter standard mode unit min. max. ic1 i2clk cycle time 10 - s ic2 hold time (repeated) start condition 4.0 - s ic3 set-up time for stop condition 4.0 - s ic4 data hold time 0 1 1 a device must internally provide a hold time of at least 300 ns for i2dat signal in order to bridge the undefined region of the falling edge of i2clk. 3.45 2 2 the maximum hold time has only to be met if the device does not stretch the low period (id no ic5) of the i2clk signal s ic5 high period of i2clk clock 4.0 - s ic6 low period of the i2clk clock 4.7 - s ic7 set-up time for a repeated start condition 4.7 - s ic8 data set-up time 250 - ns ic9 bus free time between a stop and start condition 4.7 - s ic10 rise time of both i2dat and i2clk signals - 1000 ns ic11 fall time of both i2dat and i2clk signals - 300 ns ic12 capacitive load for each bus line (c b )-400pf
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 93 3.7.12 liquid crystal display controller (lcdc) timing figure 65 and figure 66 show lcdc timing in non-tft and tft mode respectively, and table 71 and table 72 list the timing parameters used in the associated figures. figure 65. lcdc non-tft mode timing diagram table 71. lcdc non-tft mode timing parameters id description min. max. unit t1 pixel clock period 22.5 1000 ns t2 hsync width 1 ? t 1 1 t is pixel clock period t3 ld setup time 5 ? ns t4 ld hold time 5 ? ns t5 wait between hsync and vsync rising edge 2 ? t 1 t6 wait between last data and hsync rising edge 1 ? t 1 line 1 line 2 line n line 1 vsync hsync hsync lsclk ld t1 t2 t3 t4 t5 t6
i.mx25 applications processor for consumer and industrial products, rev. 9 94 freescale semiconductor figure 66. lcdc tft mode timing diagram 3.7.13 pulse width modulator (pwm) timing parameters figure 67 depicts the timing of the pwm, and table 73 lists the pwm timing characteristics. the pwm can be programmed to select one of three cl ock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse width modulator output (pwmo) external pin. table 72. lcdc tft mode timing parameters id description min. ma unit t1 pixel clock period 22.5 1000 ns t2 hsync width 1 ? t 1 1 t is pixel clock period t3 ld setup time 5 ? ns t4 ld hold time 5 ? ns t5 delay from the end of hsync to the beginning of the oe pulse 3 ? t 1 t6 delay from end of oe to the beginning of the hsync pulse 1 ? t 1 t6 oe t5 line 1 line 2 line n line 1 vsync hsync lsclk ld t1 t2 t3 t4 hsync
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 95 figure 67. pwm timing 3.7.14 subscriber identity module (sim) timing each sim module interface consists of a total of 12 pins (two separate ports, each containing six signals). typically a port uses five signals. the interface is designed to be used with synchronous sim cards, meaning the sim module provides the clock used by the sim card. the clock frequency is typically 372 times the tx/rx data rate; however, the sim module can also work with clk fre quencies of 16 times the tx/rx data rate. there is no timing relationship between the clock and the data. the clock that the sim module provides to the sim card is used by the sim card to recover the clock from the data in the same manner as standard uart data exchanges. all six signals (five for bi directional tx/rx) of the sim module are asynchronous with each other. there are no required timing relationships between signals in normal mode. the sim card is initiated by the interface device; the sim card responds with answer to reset. although the sim interface has no defined requirements, the iso/iec 7816 defines reset and power-down sequences (for detailed information see iso/iec 7816). table 73. pwm output timing parameter ref no. parameter minimum maximum unit 1 system clk frequency 1 1 cl of pwmo = 30 pf 0 ipg_clk mhz 2a clock high time 12.29 ? ns 2b clock low time 9.91 ? ns 3a clock fall time ? 0.5 ns 3b clock rise time ? 0.5 ns 4a output delay time ? 9.37 ns 4b output setup time 8.71 ? ns 4a pwm source clock 2a 1 pwm output 2b 3a 3b 4b
i.mx25 applications processor for consumer and industrial products, rev. 9 96 freescale semiconductor figure 68. sim clock timing diagram table 74 defines the general timing requirements for the sim interface. table 74. timing specifications, high drive strength id parameter symbol min. max. unit si1 sim clock frequency (simx_clky) 1 1 50% duty cycle clock, s freq 0.01 25 mhz si2 sim clock rise time (simx_clky) 2 2 with c = 50 pf s rise ?0.09 (1/s freq )ns si3 sim clock fall time (simx_clky) 3 3 with c = 50 pf s fall ?0.09 (1/s freq )ns si4 sim input transition time (simx_datay_rx_tx, simx_simpdy) s trans 10 25 ns si5 sim i/o rise time / fall time (simx_datay_rx_tx) 4 4 with cin = 30 pf, cout = 30 pf, tr / t f ? 1 s si6 sim rst rise time / fall time (simx_rsty) 5 5 with cin = 30 pf, tr / t f ? 1 s simx_clky 1 /si1 si4 si4 simx_datay_tx_rx simx_simpdy si5 si5 simx_datay_tx_rx si6 si6 simx_rsty si2 si3
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 97 3.7.14.1 sim reset sequences sim cards may have internal reset, or active low re set. the following subset describes the reset sequences in these two cases. 3.7.14.1.1 sim cards with internal reset figure 69 shows the reset sequence for sim cards with internal reset. the reset sequence comprises the following steps: ? after power-up, the clock signal is enabled on sim x _clk y (time t0) ? after 200 clock cycles, sim x _data y _rx_tx must be asserted. ? the card must send a response on sim x _data y _rx_tx acknowledging the reset between 400?40000 clock cycles after t0. figure 69. internal reset card reset sequence table 75 defines the general timing requirements for the sim interface. 3.7.14.1.2 sim cards with active low reset figure 70 shows the reset sequence for sim cards with ac tive low reset. the reset sequence comprises the following steps: ? after power-up, the clock signal is enabled on sim x _clk y (time t0) ? after 200 clock cycles, sim x _data y _rx_tx must be asserted. ?sim x _rst y must remain low for at least 40,000 clock cycles after t0 (no response is to be received on rx during those 40,000 clock cycles) ?sim x _rst y is asserted (at time t1) ?sim x _rst y must remain asserted for at least 40,000 clock cycles after t1, and a response must be received on sim x _data y _rx_tx between 400 and 40,000 clock cycles after t1. table 75. timing specifications, internal reset card reset sequence ref no. min. max. units 1 ? 200 clk cycles 2 400 40,000 clk cycles sim n _sven m simx_clky simx_datay_rx_tx 2 t0 response 1
i.mx25 applications processor for consumer and industrial products, rev. 9 98 freescale semiconductor figure 70. active-low-reset sim card reset sequence table 76 defines the general timing requirements for the sim interface. 3.7.14.2 sim power-down sequence figure 71 shows the sim interface power-down ac timing diagram. table 77 shows the timing requirements for parameters (si7?si10) shown in the figure. the power-down sequence for the sim interface is as follows: ?sim x _simpd y port detects the removal of the sim card ?sim x _rst y is negated ?sim x _clk y is negated ?sim x _data y _rx_tx is negated ?sim x _sven y is negated each of the above steps requires one ckil period (usually 32 khz). power-down may be initiated by a sim card removal detection; or it may be launched by the processor. table 76. timing specifications, active-low-reset sim card reset sequence ref no. min. max. unit 1 ? 200 clk cycles 2 400 40,000 clk cycles 3 40,000 ? clk cycles sim x _sven y sim x _clk y sim x _data y _rx_tx 2 t0 1 response sim x _rst y t1 3 3
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 99 figure 71. smartcard interface power down ac timing 3.7.15 system jtag controller (sjc) timing figure 72 through figure 75 show respectively the test clock input, boundary scan, test access port, and trst timings for the sjc. ta ble 78 describes the sjc timing paramete rs (sj1?sj13) indicated in the figures. figure 72. test clock input timing diagram table 77. timing requirements for power-down sequence id parameter symbol min. max. unit si7 sim reset to sim clock stop s rst2clk 0.9 1/fckil 1.1 1/fckil ns si8 sim reset to sim tx data low s rst2dat 1.8 1/fckil 2.2 1/fckil ns si9 sim reset to sim voltage enable low s rst2ven 2.7 1/fckil 3.3 1/fckil ns si10 sim presence detect to sim reset low s pd2rst 0.9 1/fckil 1.1 1/fckil ns simx_simpdy simx_rsty simx_clky simx_rxy & simx_txy simx_veny si7 si8 si9 si10 tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3
i.mx25 applications processor for consumer and industrial products, rev. 9 100 freescale semiconductor figure 73. boundary scan (jtag) timing diagram figure 74. test access port timing diagram tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) vih vil input data valid output data valid output data valid tms sj8 sj9 sj10 sj11 sj10
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 101 figure 75. trst timing diagram table 78. sjc timing parameters id parameter all frequencies unit min. max. sj1 tck cycle time 100 1 1 in cases where sdma tap is put in the chain, the maximum tck frequency is limited by the maximum ratio of 1:8 of sdma core frequency to tck. this implies a maximum frequency of 8.25 mhz (or 121.2 ns) for a 66 mhz ipg clock. ?ns sj2 tck clock pulse width measured at v m 2 2 v m ? mid point voltage 40 ? ns sj3 tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 10 ? ns sj5 boundary scan input data hold time 50 ? ns sj6 tck low to output data valid ? 50 ns sj7 tck low to output high impedance ? 50 ns sj8 tms, tdi data set-up time 10 ? ns sj9 tms, tdi data hold time 50 ? ns sj10 tck low to tdo data valid ? 44 ns sj11 tck low to tdo high impedance ? 44 ns sj12 trst assert time 100 ? ns sj13 trst set-up time to tck low 40 ? ns tck (input) trst (input) sj13 sj12
i.mx25 applications processor for consumer and industrial products, rev. 9 102 freescale semiconductor 3.7.16 smart liquid crystal display controller (slcdc) figure 76 and figure 77 show slcdc timing for serial and parallel transfers respectively. table 79 and table 80 describe the timing parameters shown in the respective figures. figure 76. slcdc timing diagram?serial transfers to lcd device trss trss lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data (this diagram shows the case sckpol = 1, cspol = 0) (this diagram shows the case sckpol = 0, cspol = 0) lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data (this diagram shows the case sckpol = 1, cspol = 1) lcd_clk (lcd_data[6]) sdata (lcd_data[7]) lcd_cs rs lsb msb rs=0 => command data, rs=1=> display data (this diagram shows the case sckpol = 0, cspol = 1) tcss tcyc tds tcsh tdh tcl tch trsh trss tcss tcyc tds tcsh tdh tcl tch trsh tcss tcyc tds tcsh tdh tcl tch trsh tcss tcyc tds tcsh tdh tcl tch trsh trss
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 103 figure 77. slcdc timing diagram?para llel transfers to lcd device table 79. slcdc serial interface timing parameters symbol parameter min. typ. max. units t css chip select setup time (t cyc / 2) ( ) t prop ??ns t csh chip select hold time (t cyc / 2) ( ) t prop ??ns t cyc serial clock cycle time 39 ( ) t prop ? 2641 ns t cl serial clock low pulse 18 ( ) t prop ??ns t ch serial clock high pulse 18 ( ) t prop ??ns t ds data setup time (t cyc / 2) ( ) t prop ??ns t dh data hold time (t cyc / 2) ( ) t prop ??ns t rss register select setup time (15 t cyc / 2) ( ) t prop ??ns t rsh register select hold time (t cyc / 2) ( ) t prop ??ns lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc lcd_clk lcd_data[15:0] lcd_rs command data lcd_cs display data trsh trss tds tdh tcyc (this diagram shows the case cspol=0) (this diagram shows the case cspol=1)
i.mx25 applications processor for consumer and industrial products, rev. 9 104 freescale semiconductor 3.7.17 synchronous serial interface (ssi) timing the following subsections describe ssi timing in four cases: ? transmitter with external clock ? receiver with external clock ? transmitter with internal clock ? receiver with internal clock 3.7.17.1 ssi transmitter timing with internal clock figure 78 shows the timing for ssi transmitter with internal clock, and table 81 describes the timing parameters (ss1?ss52). figure 78. ssi transmitter with internal clock timing diagram table 80. slcdc parallel interface timing parameters symbol parameter min. typ. max. units t cyc parallel clock cycle time 78 ( ) t prop ? 4923 ns t ds data setup time (t cyc / 2) ( ) t prop ??? t dh data hold time (t cyc / 2) ( ) t prop ??? t rss register select setup time (t cyc / 2) ( ) t prop ??? t rsh register select hold time (t cyc / 2) ( ) t prop ??? ss19 audn_txc audn_txfs (bl) audn_txfs (wl) ss1 audn_txd audn_rxd ss2 ss4 ss3 ss5 ss6 ss8 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 note: srxd input in synchronous mode only (output) (output) (output) (output) (input)
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 105 note: ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on pads when ssi is being used for a data transfer. ? ?tx? and ?rx? refer, respectively, to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is the same as that of tx data (for example, during ac9 7 mode of operation). table 81. ssi transmitter timing with internal clock id parameter min. max. unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss6 (tx) ck high to fs (bl) high ? 15.0 ns ss8 (tx) ck high to fs (bl) low ? 15.0 ns ss10 (tx) ck high to fs (wl) high ? 15.0 ns ss12 (tx) ck high to fs (wl) low ? 15.0 ns ss14 (tx/rx) internal fs rise time ? 6.0 ns ss15 (tx/rx) internal fs fall time ? 6.0 ns ss16 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss17 (tx) ck high to stxd high/low ? 15.0 ns ss18 (tx) ck high to stxd high impedance ? 15.0 ns ss19 stxd rise/fall time ? 6.0 ns synchronous internal clock operation ss42 srxd setup before (tx) ck falling 10.0 ? ns ss43 srxd hold after (tx) ck falling 0.0 ? ns ss52 loading ? 25.0 pf
i.mx25 applications processor for consumer and industrial products, rev. 9 106 freescale semiconductor 3.7.17.2 ssi receiver timing with internal clock figure 79 shows the timing for the ssi receiver with internal clock. table 82 describes the timing parameters (ss1?ss51) shown in the figure. figure 79. ssi receiver internal clock timing diagram table 82. ssi receiver timing with internal clock id parameter min. max. unit internal clock operation ss1 (tx/rx) ck clock period 81.4 ? ns ss2 (tx/rx) ck clock high period 36.0 ? ns ss3 (tx/rx) ck clock rise time ? 6.0 ns ss4 (tx/rx) ck clock low period 36.0 ? ns ss5 (tx/rx) ck clock fall time ? 6.0 ns ss7 (rx) ck high to fs (bl) high ? 15.0 ns ss9 (rx) ck high to fs (bl) low ? 15.0 ns ss11 (rx) ck high to fs (wl) high ? 15.0 ns ss13 (rx) ck high to fs (wl) low ? 15.0 ns ss20 srxd setup time before (rx) ck low 10.0 ? ns ss21 srxd hold time after (rx) ck low 0.0 ? ns oversampling clock operation ss47 oversampling clock period 15.04 ? ns ss50 ss48 audn_txc audn_txfs (bl) audn_txfs (wl) audn_rxd audn_rxc ss1 ss4 ss2 ss51 ss20 ss21 ss49 ss7 ss9 ss11 ss13 ss47 (output) (output) (output) (input) (output) ss3 ss5
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 107 note: ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on pads when ssi is being used for a data transfer. ? ?tx? and ?rx? refer to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is the same as that of tx data (for example, during ac9 7 mode of operation). 3.7.17.3 ssi transmitter timing with external clock figure 80 shows the timing for the ssi transmitter with external clock. table 83 describes the timing parameters (ss22-ss46) shown in the figure. figure 80. ssi transmitter with external clock timing diagram ss48 oversampling clock high period 6.0 ? ns ss49 oversampling clock rise time ? 3.0 ns ss50 oversampling clock low period 6.0 ? ns ss51 oversampling clock fall time ? 3.0 ns table 82. ssi receiver timing with internal clock (continued) id parameter min. max. unit ss45 ss24 ss26 ss25 ss23 audn_txc audn_txfs (bl) audn_txfs (wl) audn_txd audn_rxd note: srxd input in synchronous mode only ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (input) (output) (input) ss29 ss27 ss31 ss33
i.mx25 applications processor for consumer and industrial products, rev. 9 108 freescale semiconductor note: ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables figures. ? all timings are on pads when ssi is being used for data transfer. ? ?tx? and ?rx? refer, respectively, to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is the same as that of tx data (for example, during ac9 7 mode of operation). table 83. ssi transmitter timing with external clock id parameter min. max. unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss27 fs (bl) low/ high setup before (tx) ck falling ?10.0 15.0 ns ss29 fs (bl) low/ high setup before (tx) ck falling 10.0 ? ns ss31 fs (wl) low/ high setup before (tx) ck falling ?10.0 15.0 ns ss33 fs (wl) low/ high setup before (tx) ck falling 10.0 ? ns ss37 (tx) ck high to stxd valid from high impedance ? 15.0 ns ss38 (tx) ck high to stxd high/low ? 15.0 ns ss39 (tx) ck high to stxd high impedance ? 15.0 ns synchronous external clock operation ss44 srxd setup before (tx) ck falling 10.0 ? ns ss45 srxd hold after (tx) ck falling 2.0 ? ns ss46 srxd rise/fall time ? 6.0 ns
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 109 3.7.17.4 ssi receiver timing with external clock figure 81 shows the timing for ssi receiver with external clock. table 84 describes the timing parameters (ss22?ss41) used in the figure. figure 81. ssi receiver with external clock timing diagram note: ? all the timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non-inverted frame syn c (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverti ng the clock signal stck/srck and/or the frame sync stfs/srfs shown in the tables and in the figures. ? all timings are on pads when ssi is being used for data transfer. table 84. ssi receiver timing with external clock id parameter min. max. unit external clock operation ss22 (tx/rx) ck clock period 81.4 ? ns ss23 (tx/rx) ck clock high period 36.0 ? ns ss24 (tx/rx) ck clock rise time ? 6.0 ns ss25 (tx/rx) ck clock low period 36.0 ? ns ss26 (tx/rx) ck clock fall time ? 6.0 ns ss28 fs (bl) low/high setup before (tx) ck falling ?10.0 15.0 ns ss30 fs (bl) low/high setup before (tx) ck falling 10.0 ? ns ss32 fs (wl) low/high setup before (tx) ck falling ?10.0 15.0 ns ss34 fs (wl) low/high setup before (tx) ck falling 10.0 ? ns ss35 (tx/rx) external fs rise time ? 6.0 ns ss36 (tx/rx) external fs fall time ? 6.0 ns ss40 srxd setup time before (rx) ck low 10.0 ? ns ss41 srxd hold time after (rx) ck low 2.0 ? ns ss24 ss35 ss30 ss26 ss25 ss23 audn_txc audn_txfs (bl) audn_txfs (wl) audn_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) (input) ss28 ss34
i.mx25 applications processor for consumer and industrial products, rev. 9 110 freescale semiconductor ? ?tx? and ?rx? refer, respectively, to the transmit and receive sections of the ssi. ? for internal frame sync operation using external clock, the fs timing is the same as that of tx data (for example, during ac9 7 mode of operation). 3.7.18 touchscreen adc electrical specifications and timing this section describes the electrical specifications, operation modes, and timing of the touchscreen adc. 3.7.18.1 adc electrical specifications table 85 shows the electrical specifications for the touchscreen adc. table 85. touchscreen adc electrical specifications parameter conditions min. typ. max. unit adc input sampling capacitance ( c s ) no pin/pad capacitance included ? 2 ? pf resolution ? 12 bits analog bias resistance value between ref and agndref ??1.6?k timing characteristics sampling rate (fs) ? ? ? 125 khz internal adc/tsc clock frequency ? ? ? 1.75 mhz multiplexed inputs ? 8 ? data latency ? 12.5 clk cycles power-up time 1 ?14clk cycles clk falling edge to sampling delay (tsd) ?258ns soc input setup time before clk rising edge (tsocst) ?0.513ns soc input hold time after clk rising edge (tsochld) ?236ns eoc delay after clk rise edge (teoc) with a 250 pf load 2 7 10 ns valid data out delay after eoc rise edge (tdata) with a 250 pf load 5 8 13 ns power supply requirements current consumption 2 nvcc_adc qv dd ???2.1 0.5 ma ma
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 111 3.7.18.2 adc timing diagrams figure 82 represents the synchronization between the signals clk , soc , eoc, and the output bits in the usage of the internal adc. after a conversion cycle eoc is asserted, a new conversion begins only when the power-down current nvcc_adc qv dd ???1 10 ua ua touchscreen interface expected plate resistance ? 100 ? 1500 switch drivers on resistance gnd and vdd switches ? ? 10 conversion characteristics 3 dnl 4 fin = 1 khz ? +/?0.75 ? lsb inl 4 fin = 1 khz ? +/?2.0 ? lsb gain + offset error ? ? ? +/?2 %fs 1 this comprises only the required initial dummy conversion cycle. additional power-up time depends on the enadc , reset and soc signals applied to the touchscreen controller. 2 this value only includes the adc and the driver switches, but it does not take into account the current consumption in the touchscreen plate. for example, if the plate resistance is 100 w, the total current consumption is about 33 ma. 3 at avdd = 3.3 v, dvdd = 1.2 v, tjunction = 50 c, fclk = 1.75 mhz, any process corner, unless otherwise noted. 4 value measured with a ?0.5 dbfs sinusoidal input signal and computed with the code density test. table 85. touchscreen adc electrical specifications (continued) parameter conditions min. typ. max. unit
i.mx25 applications processor for consumer and industrial products, rev. 9 112 freescale semiconductor assertion of soc is detected. thus, if the soc signal is continuously asserted, the adc undergoes successive conversion cycles and achieves the maximum sampling rate. if soc is negated, no conversion is initiated. figure 82. start-up sequence the output data can be read from adcout11...adcout0 , and is available tdata nanoseconds after the rising edge of eoc . the reset signal and the digital signals controlling the analog switches ( ypsw, xpsw, ynsw, xnsw ) are totally asynchronous. the following conditions are necessary to guarantee the correct operation of the adc: ? the input multiplexer selection ( selin11?selin0 ) is stable during both the last clock cycle (14 th ) and the first clock cycle (1 st ). the best way to guarantee this is to make the input multiplexer selection during clock cycles 2 to 13. ? the references are stable during clock cycle 1 to 13. the best way to guarantee this is to make the reference multiplexer selection ( selrefp and selrefn ) before issuing an soc pulse and changing it only after an eoc pulse has been acquired, during the last clock cycle (14).
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 113 figure 83 shows the timing for adc normal operation. figure 83. timing for adc normal operation when the adc is used so that the idle clock cycles occur between conversions (due to the negation of soc ), the selin inputs must be stable at least 1 clock cycle before the clock's rising edge where the soc signal is latched. also, selrefp and selrefn must be stable by the time the soc signal is latched. these conditions are met if enadc=1 and reset=0 throughout adc operation, including the idle cycles. if the conditions are not met, or if power is lost during adc operation, then a new start-up sequence is required for adc to become operational again.
i.mx25 applications processor for consumer and industrial products, rev. 9 114 freescale semiconductor figure 84 represents the usage of the adc with idle cycles between conversions. this diagram is valid for any value of n equal or greater than 1. figure 84. adc usage with idle cycles between conversions 3.7.19 uart timing this section describes the timing of the ua rt module in serial and parallel mode.
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 115 3.7.19.1 uart rs-232 serial mode timing 3.7.19.1.1 uart transmit timing in rs-232 serial mode figure 85 shows the uart transmit timing in rs-232 serial mode, showing only 8 data bits and 1 stop bit. table 86 describes the timing parameter (ua1) shown in the figure. figure 85. uart rs-232 serial mode transmit timing diagram 3.7.19.1.2 uart receive timing in rs-232 serial mode figure 86 shows the uart receive timing in rs-232 serial mode, showing only 8 data bits and 1 stop bit. table 87 describes the timing parameter (ua2) shown in the figure. ? figure 86. uart rs-232 serial mode receive timing diagram table 86. uart rs-232 serial mode transmit timing parameters id parameter symbol min. max. units ua1 transmit bit time t tbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? table 87. uart rs-232 serial mode receive timing parameters id parameter symbol min. max. units ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rbit 1/f baud_rate 2 ? 1/(16 f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 f baud_rate ) ? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2
i.mx25 applications processor for consumer and industrial products, rev. 9 116 freescale semiconductor 3.7.19.2 uart infrared (irda) mode timing the following subsections describe the uart transmit and receive timing in irda mode. 3.7.19.2.3 uart irda mode transmit timing figure 87 depicts the uart transmit timing in irda mode, showing only 8 data bits and 1 stop bit. table 88 describes the timing parameters (ua3?ua4) shown in the figure. figure 87. uart irda mode transmit timing diagram 3.7.19.2.4 uart irda mode receive timing figure 88 shows the uart receive timing for irda mode, for a format of 8 data bits and 1 stop bit. table 89 describes the timing parameters (ua5?ua6) shown in the figure. figure 88. uart irda mode receive timing diagram table 88. uart irda mode transmit timing parameters id parameter symbol min. max. units ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 ? t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16) (1/f baud_rate ) ? t ref_clk (3/16) (1/f baud_rate ) + t ref_clk ? table 89. uart irda mode receive timing parameters id parameter symbol min. max. units ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 f baud_rate ). t rirbit 1/f baud_rate 2 ? 1/(16 f baud_rate )1/f baud_rate + 1/(16 f baud_rate )? ua6 receive ir pulse duration t rirpulse 1.41 s (5/16) (1/f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 txd (output) bit 3 start bit stop bit possible parity bit ua3 ua3 ua3 ua3 ua4 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rxd (input) bit 3 start bit stop bit possible parity bit ua5 ua5 ua5 ua5 ua6
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 117 3.7.20 usbotg timing this section describes timing for the usb otg port and host ports. both serial and parallel interfaces are described. 3.7.20.1 usb serial interface timing the usb serial transceiver is configurable to four modes supporting four different serial interfaces: ? dat_se0 bidirectional, 3-wire mode ? dat_se0 unidirectional, 6-wire mode ? vp_vm bidirectional, 4-wire mode ? vp_vm unidirectional, 6-wire mode the following subsections describe the timings for these four modes. 3.7.20.1.1 dat_se0 bidirectional mode timing table 90 defines the dat_se0 bidirectional mode signals. figure 89 shows the usb transmit waveform in dat_se0 bidirectional mode diagram. figure 89. usb transmit waveform in dat_se0 bidirectional mode 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. table 90. signal definitions?dat_se0 bidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out in tx data when usb_txoe_b is low differential rx data when usb_txoe_b is high usb_se0_vm out in se0 drive when usb_txoe_b is low se0 rx indicator when usb_txoe_b is high usb_dat_vp usb_se0_vm us1 us2 transmit us4
i.mx25 applications processor for consumer and industrial products, rev. 9 118 freescale semiconductor figure 90 shows the usb receive waveform in dat_se0 bidirectional mode diagram. figure 90. usb receive waveform in dat_se0 bidirectional mode table 91 shows the otg port timing specification in dat_se0 bidirectional mode. 3.7.20.1.2 dat_se0 unidirectional mode timing table 92 defines the dat_se0 unidirectional mode signals. table 91. otg port timing specification in dat_se0 bidirectional mode no. parameter signal name direction min. max. unit conditions/ reference signal us1 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us2 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us3 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us4 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us5 enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b us6 disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b us7 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us8 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf table 92. signal definitions?dat_se0 unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx data when usb_txoe_b is low usb_se0_vm out se0 drive when usb_txoe_b is low usb_vp1 in buffered data on dp when usb_txoe_b is high usb_vm1 in buffered data on dm when usb_txoe_b is high usb_rcv in differential rx data when usb_txoe_b is high us6 us7/us8 us5 usb_dat_vp usb_se0_vm usb_txoe_b receive
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 119 figure 91 shows the usb transmit waveform in dat_se0 unidirectional mode diagram. figure 91. usb transmit waveform in dat_se0 unidirectional mode figure 92 shows the usb receive waveform in dat_se0 unidirectional mode diagram. figure 92. usb receive waveform in dat_se0 unidirectional mode table 93 shows the usb port timing specification in dat_se0 unidirectional mode. table 93. usb port timing specification in dat_se0 unidirectional mode no. parameter signal name signal source min. max. unit condition/ reference signal us9 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us10 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us11 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us12 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us13 enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b us14 disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b us15 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us16 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us17 rx rise/fall time usb_rcv in ? 3.0 ns 35 pf usb_dat_vp usb_se0_vm us9 us10 transmit us12 us14 us17 us13 rcv usb_dat_vp usb_se0_vm receive
i.mx25 applications processor for consumer and industrial products, rev. 9 120 freescale semiconductor 3.7.20.1.3 vp_vm bidirectional mode timing table 94 defines the vp_vm bidirectional mode signals. figure 93 shows the usb transmit waveform in vp_vm bidirectional mode diagram. figure 93. usb transmit waveform in vp_vm bidirectional mode figure 94 shows the usb receive waveform in vp_vm bidirectional mode diagram. figure 94. usb receive waveform in vp_vm bidirectional mode table 94. signal definitions?vp_vm bidirectional mode name direction signal description usb_txoe_b out ? transmit enable, active low usb_dat_vp out (tx) in (rx) ? tx vp data when usb_txoe_b is low ? rx vp data when usb_txoe_b is high usb_se0_vm out (tx) in (rx) ? tx vm data when usb_txoe_b low ? rx vm data when usb_txoe_b high usb_rcv in ? differential rx data usb_vpout usb_vmout us2 us3 tra ns m it us4 usb_txenb us1 usb_vpin usb_vmin receive us5 us6
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 121 table 95 shows the usb port timing specification in vp_vm bidirectional mode. 3.7.20.1.4 vp_vm unidirectional mode timing table 96 defines the signals for usb in vp_vm unidirectional mode. table 95. usb port timing specifications in vp_vm bidirectional mode no. parameter signal name direction min. max. unit condition/ reference signal us18 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us19 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us20 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us21 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us22 tx high overlap usb_se0_vm out 0.0 ? ns usb_dat_vp us23 tx low overlap usb_se0_vm out ? 0.0 ns usb_dat_vp us24 enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b us25 disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b us26 rx rise/fall time usb_dat_vp in ? 3.0 ns 35 pf us27 rx rise/fall time usb_se0_vm in ? 3.0 ns 35 pf us28 rx skew usb_dat_vp out ?4.0 +4.0 ns usb_se0_vm us29 rx skew usb_rcv out ?6.0 +2.0 ns usb_dat_vp table 96. signal definitions for usb vp_vm unidirectional mode name direction signal description usb_txoe_b out transmit enable, active low usb_dat_vp out tx vp data when usb_txoe_b is low usb_se0_vm out tx vm data when usb_txoe_b is low usb_vp1 in rx vp data when usb_txoe_b is high usb_vm1 in rx vm data when usb_txoe_b is high usb_rcv in differential rx data
i.mx25 applications processor for consumer and industrial products, rev. 9 122 freescale semiconductor figure 95 shows the usb transmit waveform in vp_vm unidirectional mode diagram. figure 95. usb transmit waveform in vp_vm unidirectional mode figure 96 shows the usb receive waveform in vp_vm unidirectional mode diagram. figure 96. usb receive waveform in vp_vm unidirectional mode usb_dat_vp usb_se0_vm us30 us31 transmit usb_txoe_b us32 us34 us33 us37 us38 us36 usb_vm1 receive usb_rcv usb_txoe_b us41 us40 us39 usb_vp1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 123 table 97 shows the timing specifications for usb in vp_vm unidirectional mode. 3.7.20.2 usb parallel interface timing table 98 defines the usb parallel interface signals. table 97. usb timing specifications in vp_vm unidirectional mode no. parameter signal direction min. max. unit conditions/ reference signal us30 tx rise/fall time usb_dat_vp out ? 5.0 ns 50 pf us31 tx rise/fall time usb_se0_vm out ? 5.0 ns 50 pf us32 tx rise/fall time usb_txoe_b out ? 5.0 ns 50 pf us33 tx duty cycle usb_dat_vp out 49.0 51.0 % ? us34 tx high overlap usb_se0_vm out 0.0 ? ns usb_dat_vp us35 tx low overlap usb_se0_vm out ? 0.0 ns usb_dat_vp us36 enable delay usb_dat_vp usb_se0_vm in ? 8.0 ns usb_txoe_b us37 disable delay usb_dat_vp usb_se0_vm in ? 10.0 ns usb_txoe_b us38 rx rise/fall time usb_vp1 in ? 3.0 ns 35 pf us39 rx rise/fall time usb_vm1 in ? 3.0 ns 35 pf us40 rx skew usb_vp1 out ?4.0 +4.0 ns usb_se0_vm us41 rx skew usb_rcv out ?6.0 +2.0 ns usb_dat_vp table 98. signal definitions for usb parallel interface name direction signal description usb_clk in interface clock?all interface signals are synchronous to usb_clk usb_data[7:0] i/o bidirectional data bus, driven low by the link during idle?bus ownership is determined by the direction usb_dir in direction?control the direction of the data bus usb_stp out stop?the link asserts this signal for one clock cycle to stop the data stream currently on the bus usb_nxt in next?the phy asserts this signal to throttle the data
i.mx25 applications processor for consumer and industrial products, rev. 9 124 freescale semiconductor figure 97 shows the usb parallel mode transmit/receive waveform. table 99 describes the timing parameters (usb15?usb17) shown in the figure. figure 97. usb parallel mode transmit/receive waveform 4 package information and contact assignment 4.1 400 mapbga?case 17x17 mm, 0.8 mm pitch figure 98 shows the 17 17 mm i.mx25 production package. the following notes apply to figure 98 : ? all dimensions in millimeters. ? dimensioning and tolerancing per asme y14.5m-1994. ? maximum solder bump diameter measured parallel to datum a. ? datum a, the seating plane, is determined by the spherical crowns of the solder bumps. ? parallelism measurement shall exclude any effect of mark on top surface of package. table 99. usb timing specification in parallel mode id parameter min. max. unit conditions/reference signal us15 setup time (dir&nxt in, data in) 6.0 ? ns 10 pf us16 hold time (dir&nxt in, data in) 0.0 ? ns 10 pf us17 output delay time (stp out, data out ? 9.0 ns 10 pf usb_dir/nxt usb_stp us17 us16 usb_data us15 us16 us15 us17 usb_clk
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 125 figure 98. zzxz 17 17 i.mx25 production package 4.2 ground, power, sense, and reference contact assignments case 17x17 mm, 0.8 mm pitch table 100 shows the 17 17 mm package ground, power, sense, and reference contact assignments. table 100. 17 17 mm package ground, power sense, and reference contact assignments contact name contact assignment batt_vdd p10 fuse_vdd t17 mpll_gnd u17 mpll_vdd u18 ngnd_adc y13 nvcc_adc w13 nvcc_crm n14 nvcc_csi j13, j14
i.mx25 applications processor for consumer and industrial products, rev. 9 126 freescale semiconductor nvcc_dryice 1 w11 nvcc_emi1 g6, g7, g8, g9, h6, h7, h8, j6, j7 nvcc_emi2 g12, g13, g14, g15, h12, h13, h14 nvcc_jtag u10 nvcc_lcdc p6, p7, r6, r7 nvcc_misc n5, n6, n7 nvcc_nfc l6, l7, l8 nvcc_sdio r17 osc24m_gnd w15 osc24m_vdd w16 qgnd a1, a11, a20, b11, c11, d11, e5, e6, e7, e8, e9, e10, e11, e12, e13, e14, e15, e16, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, g5, g10, g16, h5, h9, h10, h11, h15, h16, j5, j9, j10, j11, j15, j16, k1, k2, k3, k4, k5, k8, k9, k10, k11, k13, k14, k15, l5, l9, l10, l11, l12, l13, l14, l15, m8, m9, m10, m11, m12, m13, m14, m15, n9, n12, n13, n15, n16, p5, p13, p14, p15, p16, r5, r8, r9, r10, r11, r12, r13, r14, r15, r16, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, y1, y20 qvdd g11, j8, j12, k6, k7, k12, m5, m6, m7, n8, p8, p9 ref v11 upll_gnd m16 upll_vdd l16 usbphy1_upllvdd m17 usbphy1_upllvss n17 usbphy1_vdda k16 usbphy1_vdda_bias k19 usbphy1_vssa l19 usbphy1_vssa_bias j17 usbphy2_vdd w18 usbphy2_vss w17 1 nvcc_dryice is a supply output. an external capacitor no less than 4 f must be connected to it. a 4.7 f capacitor is recommended. table 100. 17 17 mm package ground, power sense, and reference contact assignments (continued) contact name contact assignment
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 127 4.3 signal contact assignments?17 x 17 mm, 0.8 mm pitch table 101 lists the 17 17 mm package i.mx25 signal contact assignments. table 101. 1717 mm package i.mx25 signal contact assignment contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1 a0 a18 emi2 ddr output low a1 b17 emi2 ddr output low a2 c17 emi2 ddr output low a3 b18 emi2 ddr output low a4 c20 emi2 ddr output low a5 a19 emi2 ddr output low a6 c19 emi2 ddr output low a7 b19 emi2 ddr output low a8 d18 emi2 ddr output low a9 c18 emi2 ddr output low a10 a2 emi1 ddr output low ma10 d16 emi2 ddr output low a11 d20 emi2 ddr output low a12 d17 emi2 ddr output low a13 d19 emi2 ddr output low a14 a3 emi1 ddr output low a15 b4 emi1 ddr output low a16 c6 emi1 ddr output low a17 b5 emi1 ddr output low a18 d7 emi1 ddr output low a19 a4 emi1 ddr output low a20 b6 emi1 ddr output low a21 c7 emi1 ddr output low a22 a5 emi1 ddr output low a23 a6 emi1 ddr output low a24 b7 emi1 ddr output low a25 a7 emi1 ddr output low sd0 a12 emi1 ddr input keeper sd1 c13 emi1 ddr input keeper sd2 b13 emi1 ddr input keeper
i.mx25 applications processor for consumer and industrial products, rev. 9 128 freescale semiconductor sd3 d14 emi1 ddr input keeper sd4 d13 emi1 ddr input keeper sd5 a13 emi1 ddr input keeper sd6 d12 emi1 ddr input keeper sd7 a10 emi1 ddr input keeper sd8 b9 emi1 ddr input keeper sd9 d10 emi1 ddr input keeper sd10 b10 emi1 ddr input keeper sd11 c10 emi1 ddr input keeper sd12 c9 emi1 ddr input keeper sd13 a9 emi1 ddr input keeper sd14 d9 emi1 ddr input keeper sd15 a8 emi1 ddr input keeper sdba1 a16 emi2 ddr output low sdba0 b15 emi2 ddr output low dqm0 c12 emi1 ddr output high dqm1 c8 emi1 ddr output high ras c14 emi2 ddr output high cas c16 emi2 ddr output high sdwe a15 emi2 ddr output high sdcke0 d15 emi2 ddr output high sdcke1 c15 emi2 ddr output high sdclk b14 emi2 ddr output low sdclk_b a14 emi2 ddr output high sdqs0 b12 emi2 ddr input keeper sdqs1 b8 emi2 ddr input keeper eb0 b3 emi1 ddr output high eb1 c5 emi1 ddr output high oe d6 emi1 ddr output high cs0 c3 emi1 ddr output high cs1 d3 emi1 ddr output high cs2 b16 emi2 ddr output high table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 129 cs3 a17 emi2 ddr output high cs4 d5 emi1 gpio output high cs5 d4 emi1 gpio output high nf_ce0 d2 nfc gpio output high ecb b2 emi1 gpio input 100 k pull-up lba b1 emi1 ddr output high bclk d8 emi1 ddr output low rw c4 emi1 ddr output high nfwe_b g4 nfc gpio output high nfre_b c1 nfc gpio output high nfale f4 nfc gpio output low nfcle e4 nfc gpio output low nfwp_b h4 nfc gpio output high nfrb c2 nfc gpio input 100 k pull-up d15 j2 nfc gpio input keeper d14 j1 nfc gpio input keeper d13 h2 nfc gpio input keeper d12 h3 nfc gpio input keeper d11 f1 nfc gpio input - d10 f2 nfc gpio input keeper d9 d1 nfc gpio input keeper d8 e2 nfc gpio input keeper d7 j3 nfc gpio input keeper d6 h1 nfc gpio input keeper d5 g1 nfc gpio input keeper d4 g2 nfc gpio input keeper d3 g3 nfc gpio input keeper d2 e1 nfc gpio input keeper d1 f3 nfc gpio input keeper d0 e3 nfc gpio input keeper ld0 2 y7 lcdc gpio output low ld1 2 v8 lcdc gpio output low table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 130 freescale semiconductor ld2 2 w7 lcdc gpio output low ld3 2 u8 lcdc gpio output low ld4 2 y6 lcdc gpio output low ld5 2 v7 lcdc gpio output low ld6 2 w6 lcdc gpio output low ld7 2 y5 lcdc gpio output low ld8 2 v6 lcdc gpio output low ld9 2 w5 lcdc gpio output low ld10 2 y4 lcdc gpio output low ld11 2 y3 lcdc gpio output low ld12 2 v5 lcdc gpio output low ld13 2 w4 lcdc gpio output low ld14 2 v4 lcdc gpio output low ld15 2 w3 lcdc gpio output low hsync 2 u7 lcdc gpio output low vsync 2 u6 lcdc gpio output low lsclk 2 u5 lcdc gpio output low oe_acd 2 v3 lcdc gpio output low contrast u4 lcdc gpio output low pwm 2 w2 lcdc gpio input 100 k pull-down csi_d2 f18 csi gpio input keeper csi_d3 e19 csi gpio input keeper csi_d4 f19 csi gpio input keeper csi_d5 g18 csi gpio input keeper csi_d6 e20 csi gpio input keeper csi_d7 e18 csi gpio input keeper csi_d8 g19 csi gpio input keeper csi_d9 f20 csi gpio input keeper csi_mclk 2 h18 csi gpio output low csi_vsync 2 g20 csi gpio input keeper csi_hsync 2 h19 csi gpio input keeper csi_pixclk 2 h20 csi gpio input keeper table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 131 i2c1_clk f17 csi gpio input 100 k pull-up i2c1_dat g17 csi gpio input 100 k pull-up cspi1_mosi t4 misc gpio input 100 k pull-up cspi1_miso w1 misc gpio output low cspi1_ss0 r4 misc gpio input 100 k pull-up cspi1_ss1 v2 misc gpio input 100 k pull-up cspi1_sclk u3 misc gpio input 100 k pull-up cspi1_rdy v1 misc gpio input 100 k pull-up uart1_rxd u2 misc gpio input 100 k pull-up uart1_txd u1 misc gpio output high uart1_rts t3 misc gpio input 100 k pull-up uart1_cts t2 misc gpio output high uart2_rxd p4 misc gpio input 100 k pull-up uart2_txd t1 misc gpio output high uart2_rts r3 misc gpio input 100 k pull-up uart2_cts r2 misc gpio input - sd1_cmd k20 sdio gpio input 47 k pull-up sd1_clk m20 sdio gpio output high sd1_data0 l20 sdio gpio input 47 k pull-up sd1_data1 n20 sdio gpio input 47 k pull-up sd1_data2 m19 sdio gpio input 47 k pull-up sd1_data3 j20 sdio gpio input 47 k pull-up kpp_row0 n4 misc gpio input 100 k pull-up kpp_row1 r1 misc gpio input 100 k pull-up kpp_row2 p3 misc gpio input 100 k pull-up kpp_row3 p2 misc gpio input 100 k pull-up kpp_col0 p1 misc gpio input 100 k pull-up kpp_col1 n3 misc gpio input 100 k pull-up kpp_col2 n2 misc gpio input 100 k pull-up kpp_col3 n1 misc gpio input 100 k pull-up fec_mdc l1 misc gpio output low fec_mdio l2 misc gpio input 22 k pull-up table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 132 freescale semiconductor fec_tdata0 l3 misc gpio output high fec_tdata1 j4 misc gpio output high fec_tx_en m2 misc gpio output low fec_rdata0 m1 misc gpio input 100 k pull-down fec_rdata1 m4 misc gpio input 100 k pull-down fec_rx_dv m3 misc gpio input 100 k pull-down fec_tx_clk l4 misc gpio input 100 k pull-down rtck w10 jtag gpio output low tck v10 jtag gpio input 100 k pull-down tms y9 jtag gpio input 47 k pull-up tdi w9 jtag gpio input 47 k pull-up tdo y8 jtag gpio input - trstb v9 jtag gpio input 47 k pull-up de_b w8 jtag gpio input 47 k pull-up sjc_mod u9 jtag gpio input 100 k pull-up usbphy1_vbu s k17 usbphy1 analog analog - usbphy1_dp l18 usbphy1 analog analog - usbphy1_dm k18 usbphy1 analog analog - usbphy1_uid j18 usbphy1 analog analog - usbphy1_rre f l17 usbphy1_bias analog analog - usbphy2_dm y19 usbphy2 analog analog - usbphy2_dp y18 usbphy2 analog analog - gpio_a n19 crm gpio input - gpio_b n18 crm gpio input 100 k pull-down gpio_c p17 crm gpio input 100 k pull-down gpio_d p19 crm gpio input - gpio_e p18 crm gpio input 100 k pull-up gpio_f r19 crm gpio input - ext_armclk r20 crm gpio input - upll_bypclk u20 crm gpio input - vstby_req r18 crm gpio output low table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 133 vstby_ack 3 t20 crm gpio output low power_fail t19 crm gpio input 100 k pull-down reset_b t18 crm gpio input 100 k pull-up por_b u19 crm gpio input 100 k pull-up clko v20 crm gpio output low boot_mode0 2 v19 crm gpio input 100 k pull-down boot_mode1 2 w20 crm gpio input 100 k pull-down clk_sel w19 crm gpio input 100 k pull-down test_mode v18 crm gpio input 100 k pull-down osc24m_extal y15 osc24m analog analog - osc24m_xtal y16 osc24m analog analog - osc32k_extal y11 dryice analog analog - osc32k_xtal y10 dryice analog analog - tamper_a n10 dryice analog analog - tamper_b n11 dryice analog analog - mesh_c p11 dryice analog analog - mesh_d p12 dryice analog analog - osc_byp y12 dryice analog analog - xp v14 adc analog analog - xn u13 adc analog analog - yp v13 adc analog analog - yn w12 adc analog analog - wiper u14 adc analog analog - inaux0 u11 adc analog analog - inaux1 v12 adc analog analog - inaux2 u12 adc analog analog - 1 the state immediately after reset and before rom firmware or software has executed. 2 during power-on reset this port acts as input for fuse override signal. 3 during power-on reset this port acts as output for diagnostic signal. table 101. 1717 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 134 freescale semiconductor table 102 lists the 17 17 mm package i.mx25 no connect contact assignments. table 102. 17 17 mm package i.mx25 no connect contact assignments signal name contact assignment nc_bga_b20 b20 nc_bga_e17 e17 nc_bga_h17 h17 nc_bga_j19 j19 nc_bga_m18 m18 nc_bga_p20 p20 nc_bga_u15 u15 nc_bga_u16 u16 nc_bga_v15 v15 nc_bga_v16 v16 nc_bga_v17 v17 nc_bga_w14 w14 nc_bga_y2 y2 nc_bga_y14 y14 nc_bga_y17 y17
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 135 4.4 i.mx25 17x17 package ball map table 103 shows the i.mx25 17 17 package ball map. table 103. i.mx25 17 17 package ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a qgnd a10 a14 a19 a22 a23 a25 sd15 sd13 sd7 qgnd sd0 sd5 sdclk_b sdwe sdba1 cs3 a0 a5 qgnd b lba ecb eb0 a15 a17 a20 a24 sdqs1 sd8 sd10 qgnd sdqs0 sd2 sdclk sdba0 cs2 a1 a3 a7 nc_bga_b20 c nfre_b nfrb cs0 rw eb1 a16 a21 dqm1 sd12 sd11 qgnd dqm0 sd1 ras sdcke1 cas a2 a9 a6 a4 d d9 nf_ce0 cs1 cs5 cs4 oe a18 bclk sd14 sd9 qgnd sd6 sd4 sd3 sdcke0 ma10 a12 a8 a13 a11 e d2 d8 d0 nfcle qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd nc_bga_e17 csi_d7 csi_d3 csi_d6 f d11 d10 d1 nfale qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd i2c1_clk csi_d2 csi_d4 csi_d9 g d5 d4 d3 nfwe_b qgnd nvcc_emi1 nvcc_emi1 nvcc_emi1 nvcc_emi1 qgnd qvdd nvcc_emi2 nvcc_emi2 nvcc_emi2 nvcc_emi2 qgnd i2c1_dat csi_d5 csi_d8 csi_vsync h d6 d13 d12 nfwp_b qgnd nvcc_emi1 nvcc_emi1 nvcc_emi1 qgnd qgnd qgnd nvcc_emi2 nvcc_emi2 nvcc_emi2 qgnd qgnd nc_bga_h17 csi_mclk csi_hsync csi_pixclk j d14 d15 d7 fec_tdata1 qgnd nvcc_emi1 nvcc_emi1 qvdd qgnd qgnd qgnd qvdd nvcc_csi nvcc_csi qgnd qgnd usbphy1_vssa_bias usbphy1_uid nc_bga_j19 sd1_data3
i.mx25 applications processor for consumer and industrial products, rev. 9 136 freescale semiconductor k qgnd qgnd qgnd qgnd qgnd qvdd qvdd qgnd qgnd qgnd qgnd qvdd qgnd qgnd qgnd usbphy1_vdda usbphy1_vbus usbphy1_dm usbphy1_vdda_bias sd1_cmd l fec_mdc fec_mdio fec_tdata0 fec_tx_clk qgnd nvcc_nfc nvcc_nfc nvcc_nfc qgnd qgnd qgnd qgnd qgnd qgnd qgnd upll_vdd usbphy1_rref usbphy1_dp usbphy1_vssa sd1_data0 m fec_rdata0 fec_tx_en fec_rx_dv fec_rdata1 qvdd qvdd qvdd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd upll_gnd usbphy1_upllvdd nc_bga_m18 sd1_data2 sd1_clk n kpp_col3 kpp_col2 kpp_col1 kpp_row0 nvcc_misc nvcc_misc nvcc_misc qvdd qgnd tamper_a tamper_b qgnd qgnd nvcc_crm qgnd qgnd usbphy1_upllvss gpio_b gpio_a sd1_data1 p kpp_col0 kpp_row3 kpp_row2 uart2_rxd qgnd nvcc_lcdc nvcc_lcdc qvdd qvdd bat_vdd mesh_c mesh_d qgnd qgnd qgnd qgnd gpio_c gpio_e gpio_d nc_bga_p20 r kpp_row1 uart2_cts uart2_rts cspi1_ss0 qgnd nvcc_lcdc nvcc_lcdc qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd nvcc_sdio vstby_req gpio_f ext_armclk t uart2_txd uart1_cts uart1_rts cspi1_mosi qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd fuse_vdd reset_b power_fail vstby_ack table 103. i.mx25 17 17 package ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 137 u uart1_txd uart1_rxd cspi1_sclk contrast lsclk vsync hsync ld3 sjc_mod nvcc_jtag inaux0 inaux2 xn wiper nc_bga_u15 nc_bga_u16 mpll_gnd mpll_vdd por_b upll_bypclk v cspi1_rdy cspi1_ss1 oe_acd ld14 ld12 ld8 ld5 ld1 trstb tck ref inaux1 yp xp nc_bga_v15 nc_bga_v16 nc_bga_v17 test_mode boot_mode0 clko w cspi1_miso pwm ld15 ld13 ld9 ld6 ld2 de_b tdi rtck nvcc_dryice yn nvcc_adc nc_bga_w14 osc24m_gnd osc24m_vdd usbphy2_vss usbphy2_vdd clk_sel boot_mode1 y qgnd nc_bga_y2 ld11 ld10 ld7 ld4 ld0 tdo tms osc32k_xtal osc32k_extal osc_byp ngnd_adc nc_bga_y14 osc24m_extal osc24m_xtal nc_bga_y17 usbphy2_dp usbphy2_dm qgnd table 103. i.mx25 17 17 package ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
i.mx25 applications processor for consumer and industrial products, rev. 9 138 freescale semiconductor 4.5 347 mapbga?case 12 x 12 mm, 0.5 mm pitch figure 99 shows the 12 12 mm i.mx25 production package. the following notes apply to figure 99 : ? all dimensions in millimeters.dimensioni ng and tolerancing per asme y14.5m-1994. ? maximum solder ball diameter measured parallel to datum a. ? datum a, the seating plane, is determined by the spherical crowns of the solder balls. ? parallelism measurement shall exclude any effect of mark on package?s top surface. figure 99. 12 12 mm i.mx25 production package
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 139 4.6 ground, power, sense, and reference contact assignments case 12x12 mm, 0.5 mm pitch table 104 shows the 12 12 mm package ground, power, sense, and reference contact assignment. table 104. 12x12 mm package ground, power sense, and reference contact assignments contact name contact assignment batt_vdd aa10 fuse_vdd p18 mpll_gnd v17 mpll_vdd w19 ngnd_adc n15 nvcc_adc p15 nvcc_crm p16 nvcc_csi j15, j16 nvcc_dryice 1 r14 nvcc_emi1 g8, g9, g10, h8, h9, h10 nvcc_emi2 e15, f15, g15, g16, h15, h16 nvcc_jtag w10 nvcc_lcdc r8, r9, t8 nvcc_misc p7, p8, r7, t7 nvcc_nfc j7, j8, k7, k8 nvcc_sdio n19 osc24m_gnd t15 osc24m_vdd v15 qgnd a1, a22, b2, b14, b21, e18, f13, f14, f18, g6, g11, g12, g14, h11, h12, h14, j12, k10, k11, k12, k13, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, n10, n11, n12, n13, p11, p12, r11, r12, r18, t5, t6, t11, t12, t18, v18, v19, w2, w9, y21, aa2, aa21, ab1, ab18, ab21, ab22, j11 qvdd g7, g13, h7, h13, h18, j18, n7, n8, r10, r15, r16, t9, t10, v10, ref aa14 upll_gnd n16 upll_vdd m18 usbphy1_upllvdd l21 usbphy1_upllvss m19 usbphy1_vdda k15, k16 usbphy1_vdda_bias l22
i.mx25 applications processor for consumer and industrial products, rev. 9 140 freescale semiconductor 4.7 signal contact assignments?12 x 12 mm, 0.5 mm pitch table 105 lists the 12 12 mm package i.mx25 signal contact assignments. usbphy1_vssa k19 usbphy1_vssa_bias k18 usbphy2_vdd t16 usbphy2_vss w16 1 nvcc_dryice is a supply output. an external capacitor no less than 4 f must be connected to it. a 4.7 f capacitor is recommended. table 105. 12x12 mm package i.mx25 signal contact assignment contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1 a0 a20 emi2 ddr output low a1 a19 emi2 ddr output low a2 b18 emi2 ddr output low a3 d17 emi2 ddr output low a4 a21 emi2 ddr output low a5 b19 emi2 ddr output low a6 d18 emi2 ddr output low a7 b20 emi2 ddr output low a8 e19 emi2 ddr output low a9 d19 emi2 ddr output low a10 b5 emi1 ddr output low ma10 e17 emi2 ddr output low a11 c21 emi2 ddr output low a12 b22 emi2 ddr output low a13 d21 emi2 ddr output low a14 a4 emi1 ddr output low a15 d6 emi1 ddr output low a16 a5 emi1 ddr output low a17 e6 emi1 ddr output low a18 a6 emi1 ddr output low a19 e7 emi1 ddr output low table 104. 12x12 mm package ground, power sense, and reference contact assignments (continued) contact name contact assignment
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 141 a20 b6 emi1 ddr output low a21 d7 emi1 ddr output low a22 a7 emi1 ddr output low a23 e9 emi1 ddr output low a24 b7 emi1 ddr output low a25 d8 emi1 ddr output low sd0 a13 emi1 ddr input keeper sd1 d12 emi1 ddr input keeper sd2 b12 emi1 ddr input keeper sd3 a14 emi1 ddr input keeper sd4 b13 emi1 ddr input keeper sd5 a15 emi1 ddr input keeper sd6 b11 emi1 ddr input keeper sd7 a12 emi1 ddr input keeper sd8 d10 emi1 ddr input keeper sd9 a10 emi1 ddr input keeper sd10 a11 emi1 ddr input keeper sd11 b10 emi1 ddr input keeper sd12 b9 emi1 ddr input keeper sd13 e11 emi1 ddr input keeper sd14 b8 emi1 ddr input keeper sd15 d9 emi1 ddr input keeper sdba1 d16 emi2 ddr output low sdba0 a17 emi2 ddr output low dqm0 d11 emi1 ddr output high dqm1 a9 emi1 ddr output high ras d15 emi2 ddr output high cas b16 emi2 ddr output high sdwe b15 emi2 ddr output high sdcke0 a16 emi2 ddr output high sdcke1 f16 emi2 ddr output high sdclk d13 emi2 ddr output low table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 142 freescale semiconductor sdclk_b d14 emi2 ddr output high sdqs0 e14 emi2 ddr input keeper sdqs1 e12 emi2 ddr input keeper eb0 a2 emi1 ddr output high eb1 b4 emi1 ddr output high oe a3 emi1 ddr output high cs0 c2 emi1 ddr output high cs1 d4 emi1 ddr output high cs2 b17 emi2 ddr output high cs3 a18 emi2 ddr output high cs4 e5 emi1 gpio output high cs5 d2 emi1 gpio output high nf_ce0 f4 nfc gpio output high ecb b1 emi1 gpio input 100 k pull-up lba b3 emi1 ddr output high bclk a8 emi1 ddr output low rw d5 emi1 ddr output high nfwe_b e1 nfc gpio output high nfre_b c1 nfc gpio output high nfale e2 nfc gpio output low nfcle d1 nfc gpio output low nfwp_b g4 nfc gpio output high nfrb g5 nfc gpio input 100 k pull-up d15 k2 nfc gpio input keeper d14 k4 nfc gpio input keeper d13 j2 nfc gpio input keeper d12 j4 nfc gpio input keeper d11 k5 nfc gpio input - d10 h4 nfc gpio input keeper d9 h5 nfc gpio input keeper d8 g2 nfc gpio input keeper table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 143 d7 l1 nfc gpio input keeper d6 k1 nfc gpio input keeper d5 j1 nfc gpio input keeper d4 h2 nfc gpio input keeper d3 h1 nfc gpio input keeper d2 g1 nfc gpio input keeper d1 f1 nfc gpio input keeper d0 f2 nfc gpio input keeper ld0 2 ab10 lcdc gpio output low ld1 2 w8 lcdc gpio output low ld2 2 ab9 lcdc gpio output low ld3 2 aa9 lcdc gpio output low ld4 2 ab8 lcdc gpio output low ld5 2 aa8 lcdc gpio output low ld6 2 ab7 lcdc gpio output low ld7 2 aa7 lcdc gpio output low ld8 2 ab6 lcdc gpio output low ld9 2 aa6 lcdc gpio output low ld10 2 ab5 lcdc gpio output low ld11 2 w7 lcdc gpio output low ld12 2 ab4 lcdc gpio output low ld13 2 w6 lcdc gpio output low ld14 2 ab3 lcdc gpio output low ld15 2 aa5 lcdc gpio output low hsync 2 aa4 lcdc gpio output low vsync 2 w5 lcdc gpio output low lsclk 2 ab2 lcdc gpio output low oe_acd 2 aa3 lcdc gpio output low contrast y2 lcdc gpio output low pwm 2 w4 lcdc gpio input 100 k pull-down csi_d2 c22 csi gpio input keeper table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 144 freescale semiconductor csi_d3 f19 csi gpio input keeper csi_d4 e21 csi gpio input keeper csi_d5 g19 csi gpio input keeper csi_d6 d22 csi gpio input keeper csi_d7 f21 csi gpio input keeper csi_d8 e22 csi gpio input keeper csi_d9 h19 csi gpio input keeper csi_mclk 2 f22 csi gpio output low csi_vsync 2 g21 csi gpio input keeper csi_hsync 2 g22 csi gpio input keeper csi_pixclk 2 j19 csi gpio input keeper i2c1_clk h22 csi gpio input 100 k pull-up i2c1_dat h21 csi gpio input 100 k pull-up cspi1_mosi aa1 misc gpio input 100 k pull-up cspi1_miso v4 misc gpio output low cspi1_ss0 v2 misc gpio input 100 k pull-up cspi1_ss1 u4 misc gpio input 100 k pull-up cspi1_sclk y1 misc gpio input 100 k pull-up cspi1_rdy u5 misc gpio input 100 k pull-up uart1_rxd u2 misc gpio input 100 k pull-up uart1_txd v6 misc gpio output high uart1_rts w1 misc gpio input 100 k pull-up uart1_cts r5 misc gpio output high uart2_rxd v1 misc gpio input 100 k pull-up uart2_txd t4 misc gpio output high table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 145 uart2_rts t2 misc gpio input 100 k pull-up uart2_cts p5 misc gpio input - sd1_cmd n22 sdio gpio input 47 k pull-up sd1_clk n21 sdio gpio output high sd1_data0 p22 sdio gpio input 47 k pull-up sd1_data1 r22 sdio gpio input 47 k pull-up sd1_data2 m22 sdio gpio input 47 k pull-up sd1_data3 m21 sdio gpio input 47 k pull-up kpp_row0 r2 misc gpio input 100 k pull-up kpp_row1 r4 misc gpio input 100 k pull-up kpp_row2 u1 misc gpio input 100 k pull-up kpp_row3 p4 misc gpio input 100 k pull-up kpp_col0 t1 misc gpio input 100 k pull-up kpp_col1 n5 misc gpio input 100 k pull-up kpp_col2 p2 misc gpio input 100 k pull-up kpp_col3 n4 misc gpio input 100 k pull-up fec_mdc p1 misc gpio output low fec_mdio m2 misc gpio input 22 k pull-up fec_tdata0 l2 misc gpio output high fec_tdata1 m1 misc gpio output high fec_tx_en r1 misc gpio output low table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 146 freescale semiconductor fec_rdata0 m4 misc gpio input 100 k pull-down fec_rdata1 n2 misc gpio input 100 k pull-down fec_rx_dv l5 misc gpio input 100 k pull-down fec_tx_clk n1 misc gpio input 100 k pull-down rtck w13 jtag gpio output low tck aa13 jtag gpio input 100 k pull-down tms aa12 jtag gpio input 47 k pull-up tdi w12 jtag gpio input 47 k pull-up tdo aa11 jtag gpio input - trstb ab14 jtag gpio input 47 k pull-up de_b w11 jtag gpio input 47 k pull-up sjc_mod ab11 jtag gpio input 100 k pull-up usbphy1_vbus k22 usbphy1 analog analog - usbphy1_dp k21 usbphy1 analog analog - usbphy1_dm j21 usbphy1 analog analog - usbphy1_uid j22 usbphy1 analog analog - usbphy1_rref l19 usbphy1_bias analog analog - usbphy2_dm w18 usbphy2 analog analog - usbphy2_dp w17 usbphy2 analog analog - gpio_a t22 crm gpio input - gpio_b p21 crm gpio input 100 k pull-down gpio_c u22 crm gpio input 100 k pull-down gpio_d p19 crm gpio input - table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 147 gpio_e r21 crm gpio input 100 k pull-up gpio_f r19 crm gpio input - ext_armclk v22 crm gpio input - upll_bypclk u21 crm gpio input - vstby_req t21 crm gpio output low vstby_ack 3 w22 crm gpio output low power_fail t19 crm gpio input 100 k pull-down reset_b u19 crm gpio input 100 k pull-up por_b v21 crm gpio input 100 k pull-up clko y22 crm gpio output low boot_mode0 2 aa22 crm gpio input 100 k pull-down boot_mode1 2 w21 crm gpio input 100 k pull-down clk_sel aa20 crm gpio input 100 k pull-down test_mode aa19 crm gpio input 100 k pull-down osc24m_extal ab19 osc24m analog analog - osc24m_xtal ab20 osc24m analog analog - osc32k_extal ab13 dryice analog analog - osc32k_xtal ab12 dryice analog analog - tamper_a v11 dryice analog analog - tamper_b v13 dryice analog analog - mesh_c t13 dryice analog analog - mesh_d r13 dryice analog analog - osc_byp ab15 dryice analog analog - xp aa18 adc analog analog - xn aa16 adc analog analog - yp ab17 adc analog analog - yn w15 adc analog analog - table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 148 freescale semiconductor table 106 lists the 12 12 mm package i.mx25 no connect contact assignments. 4.8 i.mx25 12x12 package ball map table 107 shows the i.mx25 12 12 package ball map. wiper aa17 adc analog analog - inaux0 aa15 adc analog analog - inaux1 w14 adc analog analog - inaux2 ab16 adc analog analog - 1 the state immediately after reset and before rom firmware or software has executed. 2 during power-on reset this port acts as input for fuse override signal. 3 during power-on reset this port acts as output for diagnostic signal. table 106. 12 12 mm package i.mx25 no connect contact assignments signal name contact assignment nc_bga_e4 e4 nc_bga_l4 l4 table 107. i.mx25 12 12 package ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a qgnd eb0 oe a14 a16 a18 a22 bclk dqm1 sd9 sd10 sd7 sd0 sd3 sd5 sdcke0 sdba0 cs3 a1 a0 a4 qgnd b ecb qgnd lba eb1 a10 a20 a24 sd14 sd12 sd11 sd6 sd2 sd4 qgnd sdwe cas cs2 a2 a5 a7 qgnd a12 c nfre_b cs0 a11 cs1_d2 d nfcle cs5 cs1 rw a15 a21 a25 sd15 sd8 dqm0 sd1 sdclk sdclk_b ras sdba1 a3 a6 a9 a13 csi_d6 e nfwe_b nfale nc_bga_e4 cs4 a17 a19 a23 sd13 sdqs1 sdqs0 nvcc_emi2 ma10 qgnd a8 csi_d4 csi_d8 f d1 d0 nf_ce0 qgnd qgnd nvcc_emi2 sdcke1 qgnd csi_d3 csi_d7 csi_mclk table 105. 12x12 mm package i.mx25 signal contact assignment (continued) contact name contact assignment power rail i/o buffer type direction after reset 1 configuration after reset 1
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 149 g d2 d8 nfwp_b nfrb qgnd qvdd nvcc_emi1 nvcc_emi1 nvcc_emi1 qgnd qgnd qvdd qgnd nvcc_emi2 nvcc_emi2 csi_d5 csi_vsync csi_hsync h d3 d4 d10 d9 qvdd nvcc_emi1 nvcc_emi1 nvcc_emi1 qgnd qgnd qvdd qgnd nvcc_emi2 nvcc_emi2 qvdd csi_d9 i2c1_dat i2c1_clk j d5 d13 d12 nvcc_nfc nvcc_nfc qgnd qgnd nvcc_csi nvcc_csi qvdd csi_pixclk usbphy1_dm usbphy1_uid k d6 d15 d14 d11 nvcc_nfc nvcc_nfc qgnd qgnd qgnd qgnd usbphy1_vdda usbphy1_vdda usbphy1_vssa_bias usbphy1_vssa usbphy1_dp usbphy1_vbus l d7 fec_tdata0 nc_bga_l4 fec_rx_dv qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd usbphy1_rref usbphy1_upllvdd usbphy1_vdda_bias m fec_tdata1 fec_mdio fec_rdata0 qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd qgnd upll_vdd usbphy1_upllvss sd1_data3 sd1_data2 n fec_tx_clk fec_rdata1 kpp_col3 kpp_col1 qvdd qvdd qgnd qgnd qgnd qgnd ngnd_adc upll_gnd nvcc_sdio sd1_clk sd1_cmd p fec_mdc kpp_col2 kpp_row3 uart2_cts nvcc_misc nvcc_misc qgnd qgnd nvcc_adc nvcc_crm fuse_vdd gpio_d gpio_b sd1_data0 table 107. i.mx25 12 12 package ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
i.mx25 applications processor for consumer and industrial products, rev. 9 150 freescale semiconductor r fec_tx_en kpp_row0 kpp_row1 uart1_cts nvcc_misc nvcc_lcdc nvcc_lcdc qvdd qgnd qgnd mesh_d nvcc_dryice qvdd qvdd qgnd gpio_f gpio_e sd1_data1 t kpp_col0 uart2_rts uart2_txd qgnd qgnd nvcc_misc nvcc_lcdc qvdd qvdd qgnd qgnd mesh_c osc24m_gnd usbphy2_vdd qgnd power_fail vstby_req gpio_a u kpp_row2 uart1_rxd cspi1_ss1 cspi1_rdy reset_b upll_bypclk gpio_c v uart2_rxd cspi1_ss0 cspi1_miso uart1_txd qvdd tamper_a tamper_b osc24m_vdd mpll_gnd qgnd qgnd por_b ext_armclk w uart1_rts qgnd pwm vsync ld13 ld11 ld1 qgnd nvcc_jtag de_b tdi rtck inaux1 yn usbphy2_vss usbphy2_dp usbphy2_dm mpll_vdd boot_mode1 vstby_ack y cspi1_sclk contrast qgnd clko aa cspi1_mosi qgnd oe_acd hsync ld15 ld9 ld7 ld5 ld3 bat_vdd tdo tms tck ref inaux0 xn wiper xp test_mode clk_sel qgnd boot_mode0 ab qgnd lsclk ld14 ld12 ld10 ld8 ld6 ld4 ld2 ld0 sjc_mod osc32k_xtal osc32k_extal trstb osc_byp inaux2 yp qgnd osc24m_extal osc24m_xtal qgnd qgnd table 107. i.mx25 12 12 package ball map (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
i.mx25 applications processor for consumer and industrial products, rev. 9 freescale semiconductor 151 5 revision history table 108 summarizes revisions to this document. table 108. revision history rev. number date substantive change(s) rev. 9 06/2012 ? in table 1, "ordering information," on page 3 , removed exclamation marks from table rows and also removed table footnote. ?in table 3, "i.mx25 digital and analog modules," on page 6 , modified description of block mnemonic, sim. ? updated section 3.2.1, ?power-up sequence.? ? updated section 3.2.3, ?srtc dryice power-up/down sequence.? ?in figure 38 and ta b l e 5 6 : ?removed ?_b? and added an overbar to signal names, csx_b, rw_b, oe_b, eby_b, lba_b, ecb_b, and dtack_b ?changed csx and csy to cs[x] and cs[y], respectively ?in table 57, "weim asynchronous timing parameters relative to chip select table," on page 76 : ?changed we and wea to rw and rwa, respectively, for reference number, we33 ?changed we and wen to rw and rwn, respectively, for reference number, we34 ?changed rlba, rlbn, and adh to lba, lbn, and lah, respectively, for reference number, we35a ?changed rbea to ebra for reference number, we37 ?changed rben to ebrn for reference number, we38 ?changed wcsa to csa for reference numbers, we41 and we41a ?changed wlba, wlbn, and adh to lba, lbn, and lah, respectively, for reference number, we41a ?changed wbea and wben to ebwa and ebwn, respectively, for reference numbers, we45 and we46 ? updated the note after ta b l e 5 7 . ?in table 99, "usb timing specification in parallel mode," on page 124 , swapped the values of min and max columns for ids, us15 and us16. rev. 8 01/2011 ? in table 27, "ac parameters for sdram i/o," on page 36 , the frequency specification has been updated to 133 mhz. ?in table 28, "ac parameters for sdram pbijtov18_33_ddr_clk i/o," on page 37 , the frequency specification has been updated to 133 mhz. rev. 7 12/2010 ? updated the first paragraph of section 3.2.3, ?srtc dryice power-up/down sequence.? ? updated table 4, "signal considerations," on page 9 for nvcc_dryice signal. ? updated the third note for table 6, "dc operating conditions," on page 11. ? added table 9, "recommended external crystal specifications," on page 13 . ? added table 10, "recommended external reference clock specifications," on page 13 . ? added a note for the line nvcc_dryice in table 100, "17 17 mm package ground, power sense, and reference contact assignments," on page 125 . ? updated table 101, "1717 mm package i.mx25 signal contact assignment," on page 127 . ? added a note for the line nvcc_dryice in table 104, "12x12 mm package ground, power sense, and reference contact assignments," on page 139 . ? removed records for upll_bypclk, u sbphy2_dp, usbphy1rref, usbphy1_dm, usbphy1_dp, usbphy1_uid, usbphy1_vbu s, and usbphy2_dm contacts from table 104, "12x12 mm package ground, power sense, and reference contact assignments," on page 139 . ? updated table 105, "12x12 mm package i.mx25 signal contact assignment," on page 140 . rev. 6 09/2010 ? added section 3.2.3, ?srtc dryice power-up/down sequence.? rev. 5 08/2010 ? updated table 56, "weim bus timing parameters," on page 69 to include new row for we19. ? updated table 6, "dc operating conditions," on page 11 to include min and max values of fuse_vdd. rev. 4 06/2010 ? updated ta b l e 1 , ?ordering information,? to include new part numbers.
i.mx25 applications processor for consumer and industrial products, rev. 9 152 freescale semiconductor rev. 3 03/2010 ? updated ta b l e 1 , ?ordering information,? to include new part numbers. ? added ta b l e 2 , ? i.mx25 parts functional differences.? ? added section 3.3, ?power characteristics.? ? added section 4.5, ?347 mapbga?case 12 x 12 mm, 0.5 mm pitch.? ? added section 4.6, ?ground, power, sense, and reference contact assignments case 12x12 mm, 0.5 mm pitch.? ? added section 4.7, ?signal contact assignments?12 x 12 mm, 0.5 mm pitch . ? added section 4.8, ?i.mx25 12x12 package ball map.? rev. 2 12/2009 ? updated ta b l e 1 , ?ordering information,? to include new part numbers. rev. 1 10/2009 ? updated table 1, ?ordering information,? to include new part numbers. ? updated dryice description in ta ble 3 , ?i.mx25 digital and analog modules.? ? updated ref signal description in ta b l e 4 , ?signal considerations.? ? updated esd damage immunity values in ta b l e 5 , ?dc absolute maximum ratings.? ? updated values in ta b l e 1 3 , ?i.mx25 power mode current consumption.? ? added a note on timing in section 3.2.1, ?power-up sequence.? ? added ta b l e 1 4 , ?imx25 reduced power mode current consumption.? ? updated ta b l e 5 5 , ?nfc timing parameters.? ? updated values in ta b l e 5 6 , ?weim bus timing parameters. ? updated ta b l e 8 5 , ?touchscreen adc electrical specifications.? rev. 0 6/2009 initial release. table 108. revision history (continued) rev. number date substantive change(s)
document number: imx25cec rev. 9 06/2012 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale and the freescale logo are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. arm9 is a trademark of arm limited. ? 2012 freescale semiconductor, inc. all rights reserved.

▲Up To Search▲

Price & Availability of MCIMX253CJM4A

	To Download MCIMX253CJM4A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .